riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = get_field(proc->state.mstatus, MSTATUS_PRV);
  38   if (type != FETCH && get_field(proc->state.mstatus, MSTATUS_MPRV))
  39     mode = get_field(proc->state.mstatus, MSTATUS_PRV1);
  40   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  41     mode = PRV_M;
  42
  43   if (mode == PRV_M) {
  44     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  45     return addr & msb_mask;
  46   }
  47   return walk(addr, mode > PRV_U, type) | (addr & (PGSIZE-1));
  48 }
  49
  50 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  51 {
  52   reg_t paddr = translate(addr, FETCH);
  53   if (paddr >= memsz)
  54     throw trap_instruction_access_fault(addr);
  55   return (const uint16_t*)(mem + paddr);
  56 }
  57
  58 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  59 {
  60   reg_t paddr = translate(addr, LOAD);
  61   if (paddr < memsz) {
  62     memcpy(bytes, mem + paddr, len);
  63     if (!tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  64       refill_tlb(addr, paddr, LOAD);
  65   } else if (!proc || !proc->sim->mmio_load(addr, len, bytes)) {
  66     throw trap_load_access_fault(addr);
  67   }
  68 }
  69
  70 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  71 {
  72   reg_t paddr = translate(addr, STORE);
  73   if (paddr < memsz) {
  74     memcpy(mem + paddr, bytes, len);
  75     if (!tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  76       refill_tlb(addr, paddr, STORE);
  77   } else if (!proc || !proc->sim->mmio_store(addr, len, bytes)) {
  78     throw trap_store_access_fault(addr);
  79   }
  80 }
  81
  82 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  83 {
  84   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  85   reg_t expected_tag = vaddr >> PGSHIFT;
  86
  87   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  88   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  89   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  90
  91   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
  92   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
  93   else tlb_load_tag[idx] = expected_tag;
  94
  95   tlb_data[idx] = mem + paddr - vaddr;
  96 }
  97
  98 reg_t mmu_t::walk(reg_t addr, bool supervisor, access_type type)
  99 {
 100   int levels, ptidxbits, ptesize;
 101   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 102   {
 103     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 104     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 105     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 106     default: abort();
 107   }
 108
 109   // verify bits xlen-1:va_bits-1 are all equal
 110   int va_bits = PGSHIFT + levels * ptidxbits;
 111   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 112   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 113   if (masked_msbs != 0 && masked_msbs != mask)
 114     return -1;
 115
 116   reg_t base = proc->get_state()->sptbr;
 117   int ptshift = (levels - 1) * ptidxbits;
 118   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 119     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 120
 121     // check that physical address of PTE is legal
 122     reg_t pte_addr = base + idx * ptesize;
 123     if (pte_addr >= memsz)
 124       break;
 125
 126     void* ppte = mem + pte_addr;
 127     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 128     reg_t ppn = pte >> PTE_PPN_SHIFT;
 129
 130     if (PTE_TABLE(pte)) { // next level of page table
 131       base = ppn << PGSHIFT;
 132     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 133       break;
 134     } else {
 135       // set referenced and possibly dirty bits.
 136       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 137       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 138       reg_t vpn = addr >> PGSHIFT;
 139       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 140     }
 141   }
 142
 143   return -1;
 144 }
 145
 146 void mmu_t::register_memtracer(memtracer_t* t)
 147 {
 148   flush_tlb();
 149   tracer.hook(t);
 150 }