riscv/mmu.h

   1 #ifndef _RISCV_MMU_H
   2 #define _RISCV_MMU_H
   3
   4 #include "decode.h"
   5 #include "trap.h"
   6 #include "common.h"
   7 #include "processor.h"
   8
   9 class processor_t;
  10
  11 // virtual memory configuration
  12 typedef reg_t pte_t;
  13 const reg_t LEVELS = 4;
  14 const reg_t PGSHIFT = 12;
  15 const reg_t PGSIZE = 1 << PGSHIFT;
  16 const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
  17 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  18
  19 // page table entry (PTE) fields
  20 #define PTE_T    0x001 // Entry is a page Table descriptor
  21 #define PTE_E    0x002 // Entry is a page table Entry
  22 #define PTE_R    0x004 // Referenced
  23 #define PTE_D    0x008 // Dirty
  24 #define PTE_UX   0x010 // User eXecute permission
  25 #define PTE_UW   0x020 // User Read permission
  26 #define PTE_UR   0x040 // User Write permission
  27 #define PTE_SX   0x080 // Supervisor eXecute permission
  28 #define PTE_SW   0x100 // Supervisor Read permission
  29 #define PTE_SR   0x200 // Supervisor Write permission
  30 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  31 #define PTE_PERM_SHIFT 4
  32 #define PTE_PPN_SHIFT  12 // LSB of physical page number in the PTE
  33
  34 // this class implements a processor's port into the virtual memory system.
  35 // an MMU and instruction cache are maintained for simulator performance.
  36 class mmu_t
  37 {
  38 public:
  39   mmu_t(char* _mem, size_t _memsz);
  40   ~mmu_t();
  41
  42   // template for functions that load an aligned value from memory
  43   #define load_func(type) \
  44     type##_t load_##type(reg_t addr) { \
  45       if(unlikely(addr % sizeof(type##_t))) \
  46       { \
  47         badvaddr = addr; \
  48         throw trap_load_address_misaligned; \
  49       } \
  50       void* paddr = translate(addr, false, false); \
  51       return *(type##_t*)paddr; \
  52     }
  53
  54   // load value from memory at aligned address; zero extend to register width
  55   load_func(uint8)
  56   load_func(uint16)
  57   load_func(uint32)
  58   load_func(uint64)
  59
  60   // load value from memory at aligned address; sign extend to register width
  61   load_func(int8)
  62   load_func(int16)
  63   load_func(int32)
  64   load_func(int64)
  65
  66   // template for functions that store an aligned value to memory
  67   #define store_func(type) \
  68     void store_##type(reg_t addr, type##_t val) { \
  69       if(unlikely(addr % sizeof(type##_t))) \
  70       { \
  71         badvaddr = addr; \
  72         throw trap_store_address_misaligned; \
  73       } \
  74       void* paddr = translate(addr, true, false); \
  75       *(type##_t*)paddr = val; \
  76     }
  77
  78   // store value to memory at aligned address
  79   store_func(uint8)
  80   store_func(uint16)
  81   store_func(uint32)
  82   store_func(uint64)
  83
  84   // load instruction from memory at aligned address.
  85   // (needed because instruction alignment requirement is variable
  86   // if RVC is supported)
  87   // returns the instruction at the specified address, given the current
  88   // RVC mode.  func is set to a pointer to a function that knows how to
  89   // execute the returned instruction.
  90   insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc,
  91                                                   insn_func_t* func)
  92   {
  93     insn_t insn;
  94
  95     #ifdef RISCV_ENABLE_RVC
  96     if(addr % 4 == 2 && rvc) // fetch across word boundary
  97     {
  98       void* addr_lo = translate(addr, false, true);
  99       insn.bits = *(uint16_t*)addr_lo;
 100
 101       *func = processor_t::dispatch_table
 102                [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 103
 104       if(!INSN_IS_RVC(insn.bits))
 105       {
 106         void* addr_hi = translate(addr+2, false, true);
 107         insn.bits |= (uint32_t)*(uint16_t*)addr_hi << 16;
 108       }
 109     }
 110     else
 111     #endif
 112     {
 113       reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
 114       insn_t data = icache_data[idx];
 115       *func = icache_func[idx];
 116       if(likely(icache_tag[idx] == addr))
 117         return data;
 118
 119       // the processor guarantees alignment based upon rvc mode
 120       void* paddr = translate(addr, false, true);
 121       insn = *(insn_t*)paddr;
 122
 123       icache_tag[idx] = addr;
 124       icache_data[idx] = insn;
 125       icache_func[idx] = *func = processor_t::dispatch_table
 126                                  [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 127     }
 128
 129     return insn;
 130   }
 131
 132   // get the virtual address that caused a fault
 133   reg_t get_badvaddr() { return badvaddr; }
 134
 135   // get/set the page table base register
 136   reg_t get_ptbr() { return ptbr; }
 137   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
 138
 139   // keep the MMU in sync with processor mode
 140   void set_supervisor(bool sup) { supervisor = sup; }
 141   void set_vm_enabled(bool en) { vm_enabled = en; }
 142
 143   // flush the TLB and instruction cache
 144   void flush_tlb();
 145   void flush_icache();
 146
 147 private:
 148   char* mem;
 149   size_t memsz;
 150   reg_t badvaddr;
 151
 152   reg_t ptbr;
 153   bool supervisor;
 154   bool vm_enabled;
 155
 156   // implement a TLB for simulator performance
 157   static const reg_t TLB_ENTRIES = 256;
 158   long tlb_data[TLB_ENTRIES];
 159   reg_t tlb_insn_tag[TLB_ENTRIES];
 160   reg_t tlb_load_tag[TLB_ENTRIES];
 161   reg_t tlb_store_tag[TLB_ENTRIES];
 162
 163   // implement an instruction cache for simulator performance
 164   static const reg_t ICACHE_ENTRIES = 256;
 165   insn_t icache_data[ICACHE_ENTRIES];
 166   insn_func_t icache_func[ICACHE_ENTRIES];
 167   reg_t icache_tag[ICACHE_ENTRIES];
 168
 169   // finish translation on a TLB miss and upate the TLB
 170   void* refill(reg_t addr, bool store, bool fetch);
 171
 172   // perform a page table walk for a given virtual address
 173   pte_t walk(reg_t addr);
 174
 175   // translate a virtual address to a physical address
 176   void* translate(reg_t addr, bool store, bool fetch)
 177   {
 178     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 179
 180     reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
 181     reg_t expected_tag = addr & ~(PGSIZE-1);
 182     if(likely(tlb_tag[idx] == expected_tag))
 183       return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]);
 184
 185     return refill(addr, store, fetch);
 186   }
 187
 188   friend class processor_t;
 189 };
 190
 191 #endif