1 // See LICENSE for license details.
10 #include "processor.h"
11 #include "memtracer.h"
14 // virtual memory configuration
16 const reg_t LEVELS
= sizeof(pte_t
) == 8 ? 3 : 2;
17 const reg_t PTIDXBITS
= 10;
18 const reg_t PGSHIFT
= PTIDXBITS
+ (sizeof(pte_t
) == 8 ? 3 : 2);
19 const reg_t PGSIZE
= 1 << PGSHIFT
;
20 const reg_t VPN_BITS
= PTIDXBITS
* LEVELS
;
21 const reg_t PPN_BITS
= 8*sizeof(reg_t
) - PGSHIFT
;
22 const reg_t VA_BITS
= VPN_BITS
+ PGSHIFT
;
24 // this class implements a processor's port into the virtual memory system.
25 // an MMU and instruction cache are maintained for simulator performance.
29 mmu_t(char* _mem
, size_t _memsz
);
32 // template for functions that load an aligned value from memory
33 #define load_func(type) \
34 type##_t load_##type(reg_t addr) { \
35 if(unlikely(addr % sizeof(type##_t))) \
36 throw trap_load_address_misaligned(addr); \
37 reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
38 return *(type##_t*)(mem + paddr); \
41 // load value from memory at aligned address; zero extend to register width
47 // load value from memory at aligned address; sign extend to register width
53 // template for functions that store an aligned value to memory
54 #define store_func(type) \
55 void store_##type(reg_t addr, type##_t val) { \
56 if(unlikely(addr % sizeof(type##_t))) \
57 throw trap_store_address_misaligned(addr); \
58 reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
59 *(type##_t*)(mem + paddr) = val; \
62 // store value to memory at aligned address
74 // load instruction from memory at aligned address.
75 inline insn_fetch_t
load_insn(reg_t addr
)
77 reg_t idx
= (addr
/sizeof(insn_t::itype
)) % ICACHE_ENTRIES
;
78 if (unlikely(icache_tag
[idx
] != addr
))
80 reg_t paddr
= translate(addr
, sizeof(insn_t::itype
), false, true);
82 fetch
.insn
.itype
= *(decltype(insn_t::itype
)*)(mem
+ paddr
);
83 fetch
.func
= proc
->decode_insn(fetch
.insn
);
85 reg_t idx
= (paddr
/sizeof(insn_t::itype
)) % ICACHE_ENTRIES
;
86 icache_tag
[idx
] = addr
;
87 icache_data
[idx
] = fetch
;
89 if (tracer
.interested_in_range(paddr
, paddr
+ sizeof(insn_t::itype
), false, true))
92 tracer
.trace(paddr
, sizeof(insn_t::itype
), false, true);
95 return icache_data
[idx
];
98 void set_processor(processor_t
* p
) { proc
= p
; flush_tlb(); }
103 void register_memtracer(memtracer_t
*);
109 memtracer_list_t tracer
;
111 // implement an instruction cache for simulator performance
112 static const reg_t ICACHE_ENTRIES
= 256;
113 insn_fetch_t icache_data
[ICACHE_ENTRIES
];
115 // implement a TLB for simulator performance
116 static const reg_t TLB_ENTRIES
= 256;
117 reg_t tlb_data
[TLB_ENTRIES
];
118 reg_t tlb_insn_tag
[TLB_ENTRIES
];
119 reg_t tlb_load_tag
[TLB_ENTRIES
];
120 reg_t tlb_store_tag
[TLB_ENTRIES
];
121 reg_t icache_tag
[ICACHE_ENTRIES
];
123 // finish translation on a TLB miss and upate the TLB
124 reg_t
refill_tlb(reg_t addr
, reg_t bytes
, bool store
, bool fetch
);
126 // perform a page table walk for a given virtual address
127 pte_t
walk(reg_t addr
);
129 // translate a virtual address to a physical address
130 reg_t
translate(reg_t addr
, reg_t bytes
, bool store
, bool fetch
)
132 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
134 reg_t
* tlb_tag
= fetch
? tlb_insn_tag
: store
? tlb_store_tag
:tlb_load_tag
;
135 reg_t expected_tag
= addr
& ~(PGSIZE
-1);
136 if(likely(tlb_tag
[idx
] == expected_tag
))
137 return ((uintptr_t)addr
& (PGSIZE
-1)) + tlb_data
[idx
];
139 return refill_tlb(addr
, bytes
, store
, fetch
);
142 friend class processor_t
;