riscv/mmu.h

   1 #ifndef _RISCV_MMU_H
   2 #define _RISCV_MMU_H
   3
   4 #include "decode.h"
   5 #include "trap.h"
   6 #include "common.h"
   7 #include "config.h"
   8 #include "processor.h"
   9
  10 class processor_t;
  11
  12 // virtual memory configuration
  13 typedef reg_t pte_t;
  14 const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
  15 const reg_t PGSHIFT = 13;
  16 const reg_t PGSIZE = 1 << PGSHIFT;
  17 const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
  18 const reg_t VPN_BITS = PTIDXBITS * LEVELS;
  19 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  20 const reg_t VA_BITS = VPN_BITS + PGSHIFT;
  21
  22 // page table entry (PTE) fields
  23 #define PTE_T    0x001 // Entry is a page Table descriptor
  24 #define PTE_E    0x002 // Entry is a page table Entry
  25 #define PTE_R    0x004 // Referenced
  26 #define PTE_D    0x008 // Dirty
  27 #define PTE_UX   0x010 // User eXecute permission
  28 #define PTE_UW   0x020 // User Read permission
  29 #define PTE_UR   0x040 // User Write permission
  30 #define PTE_SX   0x080 // Supervisor eXecute permission
  31 #define PTE_SW   0x100 // Supervisor Read permission
  32 #define PTE_SR   0x200 // Supervisor Write permission
  33 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  34 #define PTE_PPN_SHIFT  13 // LSB of physical page number in the PTE
  35
  36 // this class implements a processor's port into the virtual memory system.
  37 // an MMU and instruction cache are maintained for simulator performance.
  38 class mmu_t
  39 {
  40 public:
  41   mmu_t(char* _mem, size_t _memsz);
  42   ~mmu_t();
  43
  44   // template for functions that load an aligned value from memory
  45   #define load_func(type) \
  46     type##_t load_##type(reg_t addr) { \
  47       if(unlikely(addr % sizeof(type##_t))) \
  48       { \
  49         badvaddr = addr; \
  50         throw trap_load_address_misaligned; \
  51       } \
  52       void* paddr = translate(addr, false, false); \
  53       return *(type##_t*)paddr; \
  54     }
  55
  56   // load value from memory at aligned address; zero extend to register width
  57   load_func(uint8)
  58   load_func(uint16)
  59   load_func(uint32)
  60   load_func(uint64)
  61
  62   // load value from memory at aligned address; sign extend to register width
  63   load_func(int8)
  64   load_func(int16)
  65   load_func(int32)
  66   load_func(int64)
  67
  68   // template for functions that store an aligned value to memory
  69   #define store_func(type) \
  70     void store_##type(reg_t addr, type##_t val) { \
  71       if(unlikely(addr % sizeof(type##_t))) \
  72       { \
  73         badvaddr = addr; \
  74         throw trap_store_address_misaligned; \
  75       } \
  76       void* paddr = translate(addr, true, false); \
  77       *(type##_t*)paddr = val; \
  78     }
  79
  80   // store value to memory at aligned address
  81   store_func(uint8)
  82   store_func(uint16)
  83   store_func(uint32)
  84   store_func(uint64)
  85
  86   // load instruction from memory at aligned address.
  87   // (needed because instruction alignment requirement is variable
  88   // if RVC is supported)
  89   // returns the instruction at the specified address, given the current
  90   // RVC mode.  func is set to a pointer to a function that knows how to
  91   // execute the returned instruction.
  92   insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc,
  93                                                   insn_func_t* func)
  94   {
  95     insn_t insn;
  96
  97     #ifdef RISCV_ENABLE_RVC
  98     if(addr % 4 == 2 && rvc) // fetch across word boundary
  99     {
 100       void* addr_lo = translate(addr, false, true);
 101       insn.bits = *(uint16_t*)addr_lo;
 102
 103       *func = processor_t::dispatch_table
 104                [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 105
 106       if(!INSN_IS_RVC(insn.bits))
 107       {
 108         void* addr_hi = translate(addr+2, false, true);
 109         insn.bits |= (uint32_t)*(uint16_t*)addr_hi << 16;
 110       }
 111     }
 112     else
 113     #endif
 114     {
 115       reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
 116       insn_t data = icache_data[idx];
 117       *func = icache_func[idx];
 118       if(likely(icache_tag[idx] == addr))
 119         return data;
 120
 121       // the processor guarantees alignment based upon rvc mode
 122       void* paddr = translate(addr, false, true);
 123       insn = *(insn_t*)paddr;
 124
 125       icache_tag[idx] = addr;
 126       icache_data[idx] = insn;
 127       icache_func[idx] = *func = processor_t::dispatch_table
 128                                  [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 129     }
 130
 131     return insn;
 132   }
 133
 134   // get the virtual address that caused a fault
 135   reg_t get_badvaddr() { return badvaddr; }
 136
 137   // get/set the page table base register
 138   reg_t get_ptbr() { return ptbr; }
 139   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
 140
 141   // keep the MMU in sync with processor mode
 142   void set_supervisor(bool sup) { supervisor = sup; }
 143   void set_vm_enabled(bool en) { vm_enabled = en; }
 144
 145   // flush the TLB and instruction cache
 146   void flush_tlb();
 147   void flush_icache();
 148
 149 private:
 150   char* mem;
 151   size_t memsz;
 152   reg_t badvaddr;
 153
 154   reg_t ptbr;
 155   bool supervisor;
 156   bool vm_enabled;
 157
 158   // implement a TLB for simulator performance
 159   static const reg_t TLB_ENTRIES = 256;
 160   long tlb_data[TLB_ENTRIES];
 161   reg_t tlb_insn_tag[TLB_ENTRIES];
 162   reg_t tlb_load_tag[TLB_ENTRIES];
 163   reg_t tlb_store_tag[TLB_ENTRIES];
 164
 165   // implement an instruction cache for simulator performance
 166   static const reg_t ICACHE_ENTRIES = 256;
 167   insn_t icache_data[ICACHE_ENTRIES];
 168   insn_func_t icache_func[ICACHE_ENTRIES];
 169   reg_t icache_tag[ICACHE_ENTRIES];
 170
 171   // finish translation on a TLB miss and upate the TLB
 172   void* refill(reg_t addr, bool store, bool fetch);
 173
 174   // perform a page table walk for a given virtual address
 175   pte_t walk(reg_t addr);
 176
 177   // translate a virtual address to a physical address
 178   void* translate(reg_t addr, bool store, bool fetch)
 179   {
 180     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 181
 182     reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
 183     reg_t expected_tag = addr & ~(PGSIZE-1);
 184     if(likely(tlb_tag[idx] == expected_tag))
 185       return (void*)(((long)addr & (PGSIZE-1)) + tlb_data[idx]);
 186
 187     return refill(addr, store, fetch);
 188   }
 189
 190   friend class processor_t;
 191 };
 192
 193 #endif