riscv/mmu.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_MMU_H
   4 #define _RISCV_MMU_H
   5
   6 #include "decode.h"
   7 #include "trap.h"
   8 #include "common.h"
   9 #include "config.h"
  10 #include "processor.h"
  11 #include "memtracer.h"
  12 #include <vector>
  13
  14 // virtual memory configuration
  15 typedef reg_t pte_t;
  16 const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
  17 const reg_t PTIDXBITS = 10;
  18 const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
  19 const reg_t PGSIZE = 1 << PGSHIFT;
  20 const reg_t VPN_BITS = PTIDXBITS * LEVELS;
  21 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  22 const reg_t VA_BITS = VPN_BITS + PGSHIFT;
  23
  24 // this class implements a processor's port into the virtual memory system.
  25 // an MMU and instruction cache are maintained for simulator performance.
  26 class mmu_t
  27 {
  28 public:
  29   mmu_t(char* _mem, size_t _memsz);
  30   ~mmu_t();
  31
  32   // template for functions that load an aligned value from memory
  33   #define load_func(type) \
  34     type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
  35       if(unlikely(addr % sizeof(type##_t))) \
  36         throw trap_load_address_misaligned(addr); \
  37       void* paddr = translate(addr, sizeof(type##_t), false, false); \
  38       return *(type##_t*)paddr; \
  39     }
  40
  41   // load value from memory at aligned address; zero extend to register width
  42   load_func(uint8)
  43   load_func(uint16)
  44   load_func(uint32)
  45   load_func(uint64)
  46
  47   // load value from memory at aligned address; sign extend to register width
  48   load_func(int8)
  49   load_func(int16)
  50   load_func(int32)
  51   load_func(int64)
  52
  53   // template for functions that store an aligned value to memory
  54   #define store_func(type) \
  55     void store_##type(reg_t addr, type##_t val) { \
  56       if(unlikely(addr % sizeof(type##_t))) \
  57         throw trap_store_address_misaligned(addr); \
  58       void* paddr = translate(addr, sizeof(type##_t), true, false); \
  59       *(type##_t*)paddr = val; \
  60     }
  61
  62   // store value to memory at aligned address
  63   store_func(uint8)
  64   store_func(uint16)
  65   store_func(uint32)
  66   store_func(uint64)
  67
  68   struct insn_fetch_t
  69   {
  70     insn_func_t func;
  71     union {
  72       insn_t insn;
  73       uint_fast32_t pad;
  74     } insn;
  75   };
  76
  77   // load instruction from memory at aligned address.
  78   inline insn_fetch_t load_insn(reg_t addr)
  79   {
  80     reg_t offset = addr & (sizeof(insn_t) * (ICACHE_ENTRIES-1));
  81     offset *= sizeof(icache_entry_t) / sizeof(insn_t);
  82     icache_entry_t* entry = (icache_entry_t*)((char*)icache + offset);
  83     insn_fetch_t data = entry->data;
  84     if (likely(entry->tag == addr))
  85       return data;
  86
  87     void* iaddr = translate(addr, sizeof(insn_t), false, true);
  88     insn_fetch_t fetch;
  89     fetch.insn.pad = *(decltype(fetch.insn.insn.bits())*)iaddr;
  90     fetch.func = proc->decode_insn(fetch.insn.insn);
  91
  92     entry->tag = addr;
  93     entry->data = fetch;
  94
  95     reg_t paddr = (char*)iaddr - mem;
  96     if (!tracer.empty() && tracer.interested_in_range(paddr, paddr + sizeof(insn_t), false, true))
  97     {
  98       entry->tag = -1;
  99       tracer.trace(paddr, sizeof(insn_t), false, true);
 100     }
 101     return entry->data;
 102   }
 103
 104   void set_processor(processor_t* p) { proc = p; flush_tlb(); }
 105
 106   void flush_tlb();
 107   void flush_icache();
 108
 109   void register_memtracer(memtracer_t*);
 110
 111 private:
 112   char* mem;
 113   size_t memsz;
 114   processor_t* proc;
 115   memtracer_list_t tracer;
 116
 117   // implement an instruction cache for simulator performance
 118   static const reg_t ICACHE_ENTRIES = 2048;
 119   struct icache_entry_t {
 120     reg_t tag;
 121     reg_t pad;
 122     insn_fetch_t data;
 123   };
 124   icache_entry_t icache[ICACHE_ENTRIES];
 125
 126   // implement a TLB for simulator performance
 127   static const reg_t TLB_ENTRIES = 256;
 128   char* tlb_data[TLB_ENTRIES];
 129   reg_t tlb_insn_tag[TLB_ENTRIES];
 130   reg_t tlb_load_tag[TLB_ENTRIES];
 131   reg_t tlb_store_tag[TLB_ENTRIES];
 132
 133   // finish translation on a TLB miss and upate the TLB
 134   void* refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
 135
 136   // perform a page table walk for a given virtual address
 137   pte_t walk(reg_t addr);
 138
 139   // translate a virtual address to a physical address
 140   void* translate(reg_t addr, reg_t bytes, bool store, bool fetch)
 141     __attribute__((always_inline))
 142   {
 143     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 144     reg_t expected_tag = addr & ~(PGSIZE-1);
 145
 146     reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
 147     void* data = tlb_data[idx] + addr;
 148     if (likely(tlb_tag[idx] == expected_tag))
 149       return data;
 150
 151     return refill_tlb(addr, bytes, store, fetch);
 152   }
 153
 154   friend class processor_t;
 155 };
 156
 157 #endif