riscv/mmu.h

   1 #ifndef _RISCV_MMU_H
   2 #define _RISCV_MMU_H
   3
   4 #include "decode.h"
   5 #include "trap.h"
   6 #include "common.h"
   7 #include "processor.h"
   8
   9 class processor_t;
  10
  11 // virtual memory configuration
  12 typedef reg_t pte_t;
  13 const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2;
  14 const reg_t PGSHIFT = 13;
  15 const reg_t PGSIZE = 1 << PGSHIFT;
  16 const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
  17 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  18
  19 // page table entry (PTE) fields
  20 #define PTE_T    0x001 // Entry is a page Table descriptor
  21 #define PTE_E    0x002 // Entry is a page table Entry
  22 #define PTE_R    0x004 // Referenced
  23 #define PTE_D    0x008 // Dirty
  24 #define PTE_UX   0x010 // User eXecute permission
  25 #define PTE_UW   0x020 // User Read permission
  26 #define PTE_UR   0x040 // User Write permission
  27 #define PTE_SX   0x080 // Supervisor eXecute permission
  28 #define PTE_SW   0x100 // Supervisor Read permission
  29 #define PTE_SR   0x200 // Supervisor Write permission
  30 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  31 #define PTE_PPN_SHIFT  13 // LSB of physical page number in the PTE
  32
  33 // this class implements a processor's port into the virtual memory system.
  34 // an MMU and instruction cache are maintained for simulator performance.
  35 class mmu_t
  36 {
  37 public:
  38   mmu_t(char* _mem, size_t _memsz);
  39   ~mmu_t();
  40
  41   // template for functions that load an aligned value from memory
  42   #define load_func(type) \
  43     type##_t load_##type(reg_t addr) { \
  44       if(unlikely(addr % sizeof(type##_t))) \
  45       { \
  46         badvaddr = addr; \
  47         throw trap_load_address_misaligned; \
  48       } \
  49       void* paddr = translate(addr, false, false); \
  50       return *(type##_t*)paddr; \
  51     }
  52
  53   // load value from memory at aligned address; zero extend to register width
  54   load_func(uint8)
  55   load_func(uint16)
  56   load_func(uint32)
  57   load_func(uint64)
  58
  59   // load value from memory at aligned address; sign extend to register width
  60   load_func(int8)
  61   load_func(int16)
  62   load_func(int32)
  63   load_func(int64)
  64
  65   // template for functions that store an aligned value to memory
  66   #define store_func(type) \
  67     void store_##type(reg_t addr, type##_t val) { \
  68       if(unlikely(addr % sizeof(type##_t))) \
  69       { \
  70         badvaddr = addr; \
  71         throw trap_store_address_misaligned; \
  72       } \
  73       void* paddr = translate(addr, true, false); \
  74       *(type##_t*)paddr = val; \
  75     }
  76
  77   // store value to memory at aligned address
  78   store_func(uint8)
  79   store_func(uint16)
  80   store_func(uint32)
  81   store_func(uint64)
  82
  83   // load instruction from memory at aligned address.
  84   // (needed because instruction alignment requirement is variable
  85   // if RVC is supported)
  86   // returns the instruction at the specified address, given the current
  87   // RVC mode.  func is set to a pointer to a function that knows how to
  88   // execute the returned instruction.
  89   insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc,
  90                                                   insn_func_t* func)
  91   {
  92     insn_t insn;
  93
  94     #ifdef RISCV_ENABLE_RVC
  95     if(addr % 4 == 2 && rvc) // fetch across word boundary
  96     {
  97       void* addr_lo = translate(addr, false, true);
  98       insn.bits = *(uint16_t*)addr_lo;
  99
 100       *func = processor_t::dispatch_table
 101                [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 102
 103       if(!INSN_IS_RVC(insn.bits))
 104       {
 105         void* addr_hi = translate(addr+2, false, true);
 106         insn.bits |= (uint32_t)*(uint16_t*)addr_hi << 16;
 107       }
 108     }
 109     else
 110     #endif
 111     {
 112       reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
 113       insn_t data = icache_data[idx];
 114       *func = icache_func[idx];
 115       if(likely(icache_tag[idx] == addr))
 116         return data;
 117
 118       // the processor guarantees alignment based upon rvc mode
 119       void* paddr = translate(addr, false, true);
 120       insn = *(insn_t*)paddr;
 121
 122       icache_tag[idx] = addr;
 123       icache_data[idx] = insn;
 124       icache_func[idx] = *func = processor_t::dispatch_table
 125                                  [insn.bits % processor_t::DISPATCH_TABLE_SIZE];
 126     }
 127
 128     return insn;
 129   }
 130
 131   // get the virtual address that caused a fault
 132   reg_t get_badvaddr() { return badvaddr; }
 133
 134   // get/set the page table base register
 135   reg_t get_ptbr() { return ptbr; }
 136   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
 137
 138   // keep the MMU in sync with processor mode
 139   void set_supervisor(bool sup) { supervisor = sup; }
 140   void set_vm_enabled(bool en) { vm_enabled = en; }
 141
 142   // flush the TLB and instruction cache
 143   void flush_tlb();
 144   void flush_icache();
 145
 146 private:
 147   char* mem;
 148   size_t memsz;
 149   reg_t badvaddr;
 150
 151   reg_t ptbr;
 152   bool supervisor;
 153   bool vm_enabled;
 154
 155   // implement a TLB for simulator performance
 156   static const reg_t TLB_ENTRIES = 256;
 157   long tlb_data[TLB_ENTRIES];
 158   reg_t tlb_insn_tag[TLB_ENTRIES];
 159   reg_t tlb_load_tag[TLB_ENTRIES];
 160   reg_t tlb_store_tag[TLB_ENTRIES];
 161
 162   // implement an instruction cache for simulator performance
 163   static const reg_t ICACHE_ENTRIES = 256;
 164   insn_t icache_data[ICACHE_ENTRIES];
 165   insn_func_t icache_func[ICACHE_ENTRIES];
 166   reg_t icache_tag[ICACHE_ENTRIES];
 167
 168   // finish translation on a TLB miss and upate the TLB
 169   void* refill(reg_t addr, bool store, bool fetch);
 170
 171   // perform a page table walk for a given virtual address
 172   pte_t walk(reg_t addr);
 173
 174   // translate a virtual address to a physical address
 175   void* translate(reg_t addr, bool store, bool fetch)
 176   {
 177     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 178
 179     reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
 180     reg_t expected_tag = addr & ~(PGSIZE-1);
 181     if(likely(tlb_tag[idx] == expected_tag))
 182       return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]);
 183
 184     return refill(addr, store, fetch);
 185   }
 186
 187   friend class processor_t;
 188 };
 189
 190 #endif