riscv/mmu.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_MMU_H
   4 #define _RISCV_MMU_H
   5
   6 #include "decode.h"
   7 #include "trap.h"
   8 #include "common.h"
   9 #include "config.h"
  10 #include "processor.h"
  11 #include "memtracer.h"
  12 #include <vector>
  13
  14 // virtual memory configuration
  15 typedef reg_t pte_t;
  16 const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
  17 const reg_t PTIDXBITS = 10;
  18 const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
  19 const reg_t PGSIZE = 1 << PGSHIFT;
  20 const reg_t VPN_BITS = PTIDXBITS * LEVELS;
  21 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  22 const reg_t VA_BITS = VPN_BITS + PGSHIFT;
  23
  24 // this class implements a processor's port into the virtual memory system.
  25 // an MMU and instruction cache are maintained for simulator performance.
  26 class mmu_t
  27 {
  28 public:
  29   mmu_t(char* _mem, size_t _memsz);
  30   ~mmu_t();
  31
  32   // template for functions that load an aligned value from memory
  33   #define load_func(type) \
  34     type##_t load_##type(reg_t addr) { \
  35       if(unlikely(addr % sizeof(type##_t))) \
  36       { \
  37         badvaddr = addr; \
  38         throw trap_load_address_misaligned; \
  39       } \
  40       reg_t paddr = translate(addr, sizeof(type##_t), false, false); \
  41       return *(type##_t*)(mem + paddr); \
  42     } \
  43     type##_t load_reserved_##type(reg_t addr) { \
  44       load_reservation = addr; \
  45       return load_##type(addr); \
  46     }
  47
  48   // load value from memory at aligned address; zero extend to register width
  49   load_func(uint8)
  50   load_func(uint16)
  51   load_func(uint32)
  52   load_func(uint64)
  53
  54   // load value from memory at aligned address; sign extend to register width
  55   load_func(int8)
  56   load_func(int16)
  57   load_func(int32)
  58   load_func(int64)
  59
  60   // template for functions that store an aligned value to memory
  61   #define store_func(type) \
  62     void store_##type(reg_t addr, type##_t val) { \
  63       if(unlikely(addr % sizeof(type##_t))) \
  64       { \
  65         badvaddr = addr; \
  66         throw trap_store_address_misaligned; \
  67       } \
  68       reg_t paddr = translate(addr, sizeof(type##_t), true, false); \
  69       *(type##_t*)(mem + paddr) = val; \
  70     } \
  71     reg_t store_conditional_##type(reg_t addr, type##_t val) { \
  72       if (addr == load_reservation) { \
  73         store_##type(addr, val); \
  74         return 0; \
  75       } else return 1; \
  76     }
  77
  78   // store value to memory at aligned address
  79   store_func(uint8)
  80   store_func(uint16)
  81   store_func(uint32)
  82   store_func(uint64)
  83
  84   struct insn_fetch_t
  85   {
  86     insn_func_t func;
  87     insn_t insn;
  88   };
  89
  90   // load instruction from memory at aligned address.
  91   inline insn_fetch_t load_insn(reg_t addr)
  92   {
  93     reg_t idx = (addr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
  94     if (unlikely(icache_tag[idx] != addr))
  95     {
  96       reg_t paddr = translate(addr, sizeof(insn_t::itype), false, true);
  97       insn_fetch_t fetch;
  98       fetch.insn.itype = *(decltype(insn_t::itype)*)(mem + paddr);
  99       fetch.func = proc->decode_insn(fetch.insn);
 100
 101       reg_t idx = (paddr/sizeof(insn_t::itype)) % ICACHE_ENTRIES;
 102       icache_tag[idx] = addr;
 103       icache_data[idx] = fetch;
 104
 105       if (tracer.interested_in_range(paddr, paddr + sizeof(insn_t::itype), false, true))
 106       {
 107         icache_tag[idx] = -1;
 108         tracer.trace(paddr, sizeof(insn_t::itype), false, true);
 109       }
 110     }
 111     return icache_data[idx];
 112   }
 113
 114   reg_t get_badvaddr() { return badvaddr; }
 115   reg_t get_ptbr() { return ptbr; }
 116   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); }
 117   void set_processor(processor_t* p) { proc = p; flush_tlb(); }
 118
 119   void flush_tlb();
 120   void flush_icache();
 121   void yield_load_reservation() { load_reservation = -1; }
 122
 123   void register_memtracer(memtracer_t*);
 124
 125 private:
 126   char* mem;
 127   size_t memsz;
 128   reg_t load_reservation;
 129   reg_t badvaddr;
 130   reg_t ptbr;
 131   processor_t* proc;
 132   memtracer_list_t tracer;
 133
 134   // implement an instruction cache for simulator performance
 135   static const reg_t ICACHE_ENTRIES = 256;
 136   insn_fetch_t icache_data[ICACHE_ENTRIES];
 137
 138   // implement a TLB for simulator performance
 139   static const reg_t TLB_ENTRIES = 256;
 140   reg_t tlb_data[TLB_ENTRIES];
 141   reg_t tlb_insn_tag[TLB_ENTRIES];
 142   reg_t tlb_load_tag[TLB_ENTRIES];
 143   reg_t tlb_store_tag[TLB_ENTRIES];
 144   reg_t icache_tag[ICACHE_ENTRIES];
 145
 146   // finish translation on a TLB miss and upate the TLB
 147   reg_t refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
 148
 149   // perform a page table walk for a given virtual address
 150   pte_t walk(reg_t addr);
 151
 152   // translate a virtual address to a physical address
 153   reg_t translate(reg_t addr, reg_t bytes, bool store, bool fetch)
 154   {
 155     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 156
 157     reg_t* tlb_tag = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
 158     reg_t expected_tag = addr & ~(PGSIZE-1);
 159     if(likely(tlb_tag[idx] == expected_tag))
 160       return ((uintptr_t)addr & (PGSIZE-1)) + tlb_data[idx];
 161
 162     return refill_tlb(addr, bytes, store, fetch);
 163   }
 164
 165   friend class processor_t;
 166 };
 167
 168 #endif