riscv/mmu.h

   1 #include "decode.h"
   2 #include "trap.h"
   3 #include "icsim.h"
   4 #include "common.h"
   5 #include <assert.h>
   6
   7 class processor_t;
   8
   9 typedef reg_t pte_t;
  10
  11 const reg_t LEVELS = 4;
  12 const reg_t PGSHIFT = 12;
  13 const reg_t PGSIZE = 1 << PGSHIFT;
  14 const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
  15 const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
  16
  17 #define PTE_T    0x001 // Entry is a page Table descriptor
  18 #define PTE_E    0x002 // Entry is a page table Entry
  19 #define PTE_R    0x004 // Referenced
  20 #define PTE_D    0x008 // Dirty
  21 #define PTE_UX   0x010 // User eXecute permission
  22 #define PTE_UW   0x020 // User Read permission
  23 #define PTE_UR   0x040 // User Write permission
  24 #define PTE_SX   0x080 // Supervisor eXecute permission
  25 #define PTE_SW   0x100 // Supervisor Read permission
  26 #define PTE_SR   0x200 // Supervisor Write permission
  27 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  28 #define PTE_PERM_SHIFT 4
  29 #define PTE_PPN_SHIFT  12
  30
  31 class mmu_t
  32 {
  33 public:
  34   mmu_t(char* _mem, size_t _memsz)
  35    : mem(_mem), memsz(_memsz), badvaddr(0),
  36      ptbr(0), supervisor(true), vm_enabled(false),
  37      icsim(NULL), dcsim(NULL), itlbsim(NULL), dtlbsim(NULL)
  38   {
  39   }
  40
  41   #ifdef RISCV_ENABLE_ICSIM
  42   # define dcsim_tick(dcsim, dtlbsim, addr, size, st) \
  43       do { if(dcsim) (dcsim)->tick(addr, size, st); \
  44            if(dtlbsim) (dtlbsim)->tick(addr, sizeof(reg_t), false); } while(0)
  45   #else
  46   # define dcsim_tick(dcsim, dtlbsim, addr, size, st)
  47   #endif
  48
  49   #define load_func(type) \
  50     type##_t load_##type(reg_t addr) { \
  51       check_align(addr, sizeof(type##_t), false, false); \
  52       addr = translate(addr, false, false); \
  53       dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), false); \
  54       return *(type##_t*)(mem+addr); \
  55     }
  56
  57   #define store_func(type) \
  58     void store_##type(reg_t addr, type##_t val) { \
  59       check_align(addr, sizeof(type##_t), true, false); \
  60       addr = translate(addr, true, false); \
  61       dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), true); \
  62       *(type##_t*)(mem+addr) = val; \
  63     }
  64
  65   insn_t __attribute__((always_inline)) load_insn(reg_t addr, bool rvc)
  66   {
  67     insn_t insn;
  68
  69     reg_t idx = (addr/sizeof(insn_t)) % ICACHE_ENTRIES;
  70     bool hit = addr % 4 == 0 && icache_tag[idx] == (addr | 1);
  71     if(likely(hit))
  72       return icache_data[idx];
  73
  74     #ifdef RISCV_ENABLE_RVC
  75     if(addr % 4 == 2 && rvc)
  76     {
  77       reg_t paddr_lo = translate(addr, false, true);
  78       insn.bits = *(uint16_t*)(mem+paddr_lo);
  79
  80       if(!INSN_IS_RVC(insn.bits))
  81       {
  82         reg_t paddr_hi = translate(addr+2, false, true);
  83         insn.bits |= (uint32_t)*(uint16_t*)(mem+paddr_hi) << 16;
  84       }
  85     }
  86     else
  87     #endif
  88     {
  89       check_align(addr, 4, false, true);
  90       reg_t paddr = translate(addr, false, true);
  91       insn = *(insn_t*)(mem+paddr);
  92
  93       icache_tag[idx] = addr | 1;
  94       icache_data[idx] = insn;
  95     }
  96
  97     #ifdef RISCV_ENABLE_ICSIM
  98     if(icsim)
  99       icsim->tick(addr, insn_length(insn.bits), false);
 100     if(itlbsim)
 101       itlbsim->tick(addr, sizeof(reg_t), false);
 102     #endif
 103
 104     return insn;
 105   }
 106
 107   load_func(uint8)
 108   load_func(uint16)
 109   load_func(uint32)
 110   load_func(uint64)
 111
 112   load_func(int8)
 113   load_func(int16)
 114   load_func(int32)
 115   load_func(int64)
 116
 117   store_func(uint8)
 118   store_func(uint16)
 119   store_func(uint32)
 120   store_func(uint64)
 121
 122   reg_t get_badvaddr() { return badvaddr; }
 123   reg_t get_ptbr() { return ptbr; }
 124
 125   void set_supervisor(bool sup) { supervisor = sup; }
 126   void set_vm_enabled(bool en) { vm_enabled = en; }
 127   void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); }
 128
 129   void set_icsim(icsim_t* _icsim) { icsim = _icsim; }
 130   void set_dcsim(icsim_t* _dcsim) { dcsim = _dcsim; }
 131   void set_itlbsim(icsim_t* _itlbsim) { itlbsim = _itlbsim; }
 132   void set_dtlbsim(icsim_t* _dtlbsim) { dtlbsim = _dtlbsim; }
 133
 134   void flush_tlb();
 135   void flush_icache();
 136
 137 private:
 138   char* mem;
 139   size_t memsz;
 140   reg_t badvaddr;
 141
 142   reg_t ptbr;
 143   bool supervisor;
 144   bool vm_enabled;
 145
 146   static const reg_t TLB_ENTRIES = 256;
 147   pte_t tlb_data[TLB_ENTRIES];
 148   reg_t tlb_tag[TLB_ENTRIES];
 149
 150   static const reg_t ICACHE_ENTRIES = 256;
 151   insn_t icache_data[ICACHE_ENTRIES];
 152   reg_t icache_tag[ICACHE_ENTRIES];
 153
 154   icsim_t* icsim;
 155   icsim_t* dcsim;
 156   icsim_t* itlbsim;
 157   icsim_t* dtlbsim;
 158
 159   void check_align(reg_t addr, int size, bool store, bool fetch)
 160   {
 161     if(unlikely(addr & (size-1)))
 162     {
 163       badvaddr = addr;
 164       if(fetch)
 165         throw trap_instruction_address_misaligned;
 166       if(store)
 167         throw trap_store_address_misaligned;
 168       throw trap_load_address_misaligned;
 169     }
 170   }
 171
 172   reg_t translate(reg_t addr, bool store, bool fetch)
 173   {
 174     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
 175     pte_t pte = tlb_data[idx];
 176     reg_t tag = tlb_tag[idx];
 177
 178     trap_t trap = store ? trap_store_access_fault
 179                 : fetch ? trap_instruction_access_fault
 180                 :         trap_load_access_fault;
 181
 182     bool hit = (pte & PTE_E) && tag == (addr >> PGSHIFT);
 183     if(unlikely(!hit))
 184     {
 185       pte = walk(addr);
 186       if(!(pte & PTE_E))
 187         throw trap;
 188
 189       tlb_data[idx] = pte;
 190       tlb_tag[idx] = addr >> PGSHIFT;
 191     }
 192
 193     reg_t access_type = store ? PTE_UW : fetch ? PTE_UX : PTE_UR;
 194     if(supervisor)
 195       access_type <<= 3;
 196     if(unlikely(!(access_type & pte & PTE_PERM)))
 197       throw trap;
 198
 199     return (addr & (PGSIZE-1)) | ((pte >> PTE_PPN_SHIFT) << PGSHIFT);
 200   }
 201
 202   pte_t walk(reg_t addr)
 203   {
 204     pte_t pte = 0;
 205
 206     if(!vm_enabled)
 207     {
 208       if(addr < memsz)
 209         pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
 210     }
 211     else
 212     {
 213       reg_t base = ptbr;
 214       reg_t ptd;
 215
 216       int ptshift = (LEVELS-1)*PTIDXBITS;
 217       for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
 218       {
 219         reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
 220
 221         reg_t pte_addr = base + idx*sizeof(pte_t);
 222         if(pte_addr >= memsz)
 223           break;
 224
 225         ptd = *(pte_t*)(mem+pte_addr);
 226         if(ptd & PTE_E)
 227         {
 228           // if this PTE is from a larger PT, fake a leaf
 229           // PTE so the TLB will work right
 230           reg_t vpn = addr >> PGSHIFT;
 231           pte |= ptd | (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
 232           break;
 233         }
 234         else if(!(ptd & PTE_T))
 235           break;
 236
 237         base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
 238       }
 239     }
 240
 241     return pte;
 242   }
 243
 244   friend class processor_t;
 245 };