Fix debug reset.
[riscv-isa-sim.git] / riscv / mulhi.h
1 // See LICENSE for license details.
2
3 #ifndef _RISCV_MULHI_H
4 #define _RISCV_MULHI_H
5
6 #include <cstdint>
7
8 inline uint64_t mulhu(uint64_t a, uint64_t b)
9 {
10 uint64_t t;
11 uint32_t y1, y2, y3;
12 uint64_t a0 = (uint32_t)a, a1 = a >> 32;
13 uint64_t b0 = (uint32_t)b, b1 = b >> 32;
14
15 t = a1*b0 + ((a0*b0) >> 32);
16 y1 = t;
17 y2 = t >> 32;
18
19 t = a0*b1 + y1;
20 y1 = t;
21
22 t = a1*b1 + y2 + (t >> 32);
23 y2 = t;
24 y3 = t >> 32;
25
26 return ((uint64_t)y3 << 32) | y2;
27 }
28
29 inline int64_t mulh(int64_t a, int64_t b)
30 {
31 int negate = (a < 0) != (b < 0);
32 uint64_t res = mulhu(a < 0 ? -a : a, b < 0 ? -b : b);
33 return negate ? ~res + (a * b == 0) : res;
34 }
35
36 inline int64_t mulhsu(int64_t a, uint64_t b)
37 {
38 int negate = a < 0;
39 uint64_t res = mulhu(a < 0 ? -a : a, b);
40 return negate ? ~res + (a * b == 0) : res;
41 }
42
43 #endif