riscv/pcr.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_PCR_H
   4 #define _RISCV_PCR_H
   5
   6 #define SR_ET    0x00000001
   7 #define SR_EF    0x00000002
   8 #define SR_EV    0x00000004
   9 #define SR_EC    0x00000008
  10 #define SR_PS    0x00000010
  11 #define SR_S     0x00000020
  12 #define SR_U64   0x00000040
  13 #define SR_S64   0x00000080
  14 #define SR_VM    0x00000100
  15 #define SR_IM    0x00FF0000
  16 #define SR_IP    0xFF000000
  17 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM|SR_IP)
  18 #define SR_IM_SHIFT 16
  19 #define SR_IP_SHIFT 24
  20
  21 #define PCR_SR       0
  22 #define PCR_EPC      1
  23 #define PCR_BADVADDR 2
  24 #define PCR_EVEC     3
  25 #define PCR_COUNT    4
  26 #define PCR_COMPARE  5
  27 #define PCR_CAUSE    6
  28 #define PCR_PTBR     7
  29 #define PCR_SEND_IPI 8
  30 #define PCR_CLR_IPI  9
  31 #define PCR_COREID   10
  32 #define PCR_IMPL     11
  33 #define PCR_K0       12
  34 #define PCR_K1       13
  35 #define PCR_VECBANK  18
  36 #define PCR_VECCFG   19
  37 #define PCR_RESET    29
  38 #define PCR_TOHOST   30
  39 #define PCR_FROMHOST 31
  40
  41 #define IRQ_IPI   5
  42 #define IRQ_HOST  6
  43 #define IRQ_TIMER 7
  44
  45 #define CAUSE_MISALIGNED_FETCH 0
  46 #define CAUSE_FAULT_FETCH 1
  47 #define CAUSE_ILLEGAL_INSTRUCTION 2
  48 #define CAUSE_PRIVILEGED_INSTRUCTION 3
  49 #define CAUSE_FP_DISABLED 4
  50 #define CAUSE_SYSCALL 6
  51 #define CAUSE_BREAKPOINT 7
  52 #define CAUSE_MISALIGNED_LOAD 8
  53 #define CAUSE_MISALIGNED_STORE 9
  54 #define CAUSE_FAULT_LOAD 10
  55 #define CAUSE_FAULT_STORE 11
  56 #define CAUSE_VECTOR_DISABLED 12
  57 #define CAUSE_VECTOR_BANK 13
  58
  59 #define CAUSE_VECTOR_MISALIGNED_FETCH 24
  60 #define CAUSE_VECTOR_FAULT_FETCH 25
  61 #define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
  62 #define CAUSE_VECTOR_ILLEGAL_COMMAND 27
  63 #define CAUSE_VECTOR_MISALIGNED_LOAD 28
  64 #define CAUSE_VECTOR_MISALIGNED_STORE 29
  65 #define CAUSE_VECTOR_FAULT_LOAD 30
  66 #define CAUSE_VECTOR_FAULT_STORE 31
  67
  68 #ifdef __riscv
  69
  70 #define ASM_CR(r)   _ASM_CR(r)
  71 #define _ASM_CR(r)  cr##r
  72
  73 #ifndef __ASSEMBLER__
  74
  75 #define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
  76           asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
  77           __tmp2; })
  78
  79 #define mfpcr(reg) ({ long __tmp; \
  80           asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
  81           __tmp; })
  82
  83 #define setpcr(reg,val) ({ long __tmp; \
  84           asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
  85           __tmp; })
  86
  87 #define clearpcr(reg,val) ({ long __tmp; \
  88           asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
  89           __tmp; })
  90
  91 #endif
  92
  93 #endif
  94
  95 #endif