riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include "trap.h"
   9 #include <string>
  10 #include <vector>
  11 #include <map>
  12 #include "debug_rom/debug_rom_defines.h"
  13
  14 class processor_t;
  15 class mmu_t;
  16 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  17 class sim_t;
  18 class trap_t;
  19 class extension_t;
  20 class disassembler_t;
  21
  22 struct insn_desc_t
  23 {
  24   insn_bits_t match;
  25   insn_bits_t mask;
  26   insn_func_t rv32;
  27   insn_func_t rv64;
  28 };
  29
  30 struct commit_log_reg_t
  31 {
  32   reg_t addr;
  33   freg_t data;
  34 };
  35
  36 typedef struct
  37 {
  38   uint8_t prv;
  39   bool step;
  40   bool ebreakm;
  41   bool ebreakh;
  42   bool ebreaks;
  43   bool ebreaku;
  44   bool halt;
  45   uint8_t cause;
  46 } dcsr_t;
  47
  48 typedef enum
  49 {
  50   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
  51   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
  52   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
  53   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
  54   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
  55 } mcontrol_action_t;
  56
  57 typedef enum
  58 {
  59   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
  60   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
  61   MATCH_GE = MCONTROL_MATCH_GE,
  62   MATCH_LT = MCONTROL_MATCH_LT,
  63   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
  64   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
  65 } mcontrol_match_t;
  66
  67 typedef struct
  68 {
  69   uint8_t type;
  70   bool dmode;
  71   uint8_t maskmax;
  72   bool select;
  73   bool timing;
  74   mcontrol_action_t action;
  75   bool chain;
  76   mcontrol_match_t match;
  77   bool m;
  78   bool h;
  79   bool s;
  80   bool u;
  81   bool execute;
  82   bool store;
  83   bool load;
  84 } mcontrol_t;
  85
  86 // architectural state of a RISC-V hart
  87 struct state_t
  88 {
  89   void reset();
  90
  91   static const int num_triggers = 4;
  92
  93   reg_t pc;
  94   regfile_t<reg_t, NXPR, true> XPR;
  95   regfile_t<freg_t, NFPR, false> FPR;
  96
  97   // control and status registers
  98   reg_t prv;    // TODO: Can this be an enum instead?
  99   reg_t mstatus;
 100   reg_t mepc;
 101   reg_t mtval;
 102   reg_t mscratch;
 103   reg_t mtvec;
 104   reg_t mcause;
 105   reg_t minstret;
 106   reg_t mie;
 107   reg_t mip;
 108   reg_t medeleg;
 109   reg_t mideleg;
 110   uint32_t mcounteren;
 111   uint32_t scounteren;
 112   reg_t sepc;
 113   reg_t stval;
 114   reg_t sscratch;
 115   reg_t stvec;
 116   reg_t satp;
 117   reg_t scause;
 118   reg_t dpc;
 119   reg_t dscratch;
 120   dcsr_t dcsr;
 121   reg_t tselect;
 122   mcontrol_t mcontrol[num_triggers];
 123   reg_t tdata2[num_triggers];
 124
 125   uint32_t fflags;
 126   uint32_t frm;
 127   bool serialized; // whether timer CSRs are in a well-defined state
 128
 129   // When true, execute a single instruction and then enter debug mode.  This
 130   // can only be set by executing dret.
 131   enum {
 132       STEP_NONE,
 133       STEP_STEPPING,
 134       STEP_STEPPED
 135   } single_step;
 136
 137   reg_t load_reservation;
 138
 139 #ifdef RISCV_ENABLE_COMMITLOG
 140   commit_log_reg_t log_reg_write;
 141   reg_t last_inst_priv;
 142   int last_inst_xlen;
 143   int last_inst_flen;
 144 #endif
 145 };
 146
 147 typedef enum {
 148   OPERATION_EXECUTE,
 149   OPERATION_STORE,
 150   OPERATION_LOAD,
 151 } trigger_operation_t;
 152
 153 // Count number of contiguous 1 bits starting from the LSB.
 154 static int cto(reg_t val)
 155 {
 156   int res = 0;
 157   while ((val & 1) == 1)
 158     val >>= 1, res++;
 159   return res;
 160 }
 161
 162 // this class represents one processor in a RISC-V machine.
 163 class processor_t : public abstract_device_t
 164 {
 165 public:
 166   processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
 167   ~processor_t();
 168
 169   void set_debug(bool value);
 170   void set_histogram(bool value);
 171   void reset();
 172   void step(size_t n); // run for n cycles
 173   void set_csr(int which, reg_t val);
 174   reg_t get_csr(int which);
 175   mmu_t* get_mmu() { return mmu; }
 176   state_t* get_state() { return &state; }
 177   unsigned get_xlen() { return xlen; }
 178   unsigned get_flen() {
 179     return supports_extension('Q') ? 128 :
 180            supports_extension('D') ? 64 :
 181            supports_extension('F') ? 32 : 0;
 182   }
 183   extension_t* get_extension() { return ext; }
 184   bool supports_extension(unsigned char ext) {
 185     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 186     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 187   }
 188   void check_pc_alignment(reg_t pc) {
 189     if (unlikely(pc & 2) && !supports_extension('C'))
 190       throw trap_instruction_address_misaligned(pc);
 191   }
 192   reg_t legalize_privilege(reg_t);
 193   void set_privilege(reg_t);
 194   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 195   void update_histogram(reg_t pc);
 196   const disassembler_t* get_disassembler() { return disassembler; }
 197
 198   void register_insn(insn_desc_t);
 199   void register_extension(extension_t*);
 200
 201   // MMIO slave interface
 202   bool load(reg_t addr, size_t len, uint8_t* bytes);
 203   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 204
 205   // When true, display disassembly of each instruction that's executed.
 206   bool debug;
 207   // When true, take the slow simulation path.
 208   bool slow_path();
 209   bool halted() { return state.dcsr.cause ? true : false; }
 210   bool halt_request;
 211
 212   // Return the index of a trigger that matched, or -1.
 213   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
 214   {
 215     if (state.dcsr.cause)
 216       return -1;
 217
 218     bool chain_ok = true;
 219
 220     for (unsigned int i = 0; i < state.num_triggers; i++) {
 221       if (!chain_ok) {
 222         chain_ok |= !state.mcontrol[i].chain;
 223         continue;
 224       }
 225
 226       if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
 227           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
 228           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
 229           (state.prv == PRV_M && !state.mcontrol[i].m) ||
 230           (state.prv == PRV_S && !state.mcontrol[i].s) ||
 231           (state.prv == PRV_U && !state.mcontrol[i].u)) {
 232         continue;
 233       }
 234
 235       reg_t value;
 236       if (state.mcontrol[i].select) {
 237         value = data;
 238       } else {
 239         value = address;
 240       }
 241
 242       // We need this because in 32-bit mode sometimes the PC bits get sign
 243       // extended.
 244       if (xlen == 32) {
 245         value &= 0xffffffff;
 246       }
 247
 248       switch (state.mcontrol[i].match) {
 249         case MATCH_EQUAL:
 250           if (value != state.tdata2[i])
 251             continue;
 252           break;
 253         case MATCH_NAPOT:
 254           {
 255             reg_t mask = ~((1 << cto(state.tdata2[i])) - 1);
 256             if ((value & mask) != (state.tdata2[i] & mask))
 257               continue;
 258           }
 259           break;
 260         case MATCH_GE:
 261           if (value < state.tdata2[i])
 262             continue;
 263           break;
 264         case MATCH_LT:
 265           if (value >= state.tdata2[i])
 266             continue;
 267           break;
 268         case MATCH_MASK_LOW:
 269           {
 270             reg_t mask = state.tdata2[i] >> (xlen/2);
 271             if ((value & mask) != (state.tdata2[i] & mask))
 272               continue;
 273           }
 274           break;
 275         case MATCH_MASK_HIGH:
 276           {
 277             reg_t mask = state.tdata2[i] >> (xlen/2);
 278             if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask))
 279               continue;
 280           }
 281           break;
 282       }
 283
 284       if (!state.mcontrol[i].chain) {
 285         return i;
 286       }
 287       chain_ok = true;
 288     }
 289     return -1;
 290   }
 291
 292   void trigger_updated();
 293
 294 private:
 295   sim_t* sim;
 296   mmu_t* mmu; // main memory is always accessed via the mmu
 297   extension_t* ext;
 298   disassembler_t* disassembler;
 299   state_t state;
 300   uint32_t id;
 301   unsigned max_xlen;
 302   unsigned xlen;
 303   reg_t isa;
 304   reg_t max_isa;
 305   std::string isa_string;
 306   bool histogram_enabled;
 307   bool halt_on_reset;
 308
 309   std::vector<insn_desc_t> instructions;
 310   std::map<reg_t,uint64_t> pc_histogram;
 311
 312   static const size_t OPCODE_CACHE_SIZE = 8191;
 313   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 314
 315   void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
 316   void take_interrupt(reg_t mask); // take first enabled interrupt in mask
 317   void take_trap(trap_t& t, reg_t epc); // take an exception
 318   void disasm(insn_t insn); // disassemble and print an instruction
 319   int paddr_bits();
 320
 321   void enter_debug_mode(uint8_t cause);
 322
 323   friend class sim_t;
 324   friend class mmu_t;
 325   friend class clint_t;
 326   friend class extension_t;
 327
 328   void parse_isa_string(const char* isa);
 329   void build_opcode_map();
 330   void register_base_instructions();
 331   insn_func_t decode_insn(insn_t insn);
 332
 333   // Track repeated executions for processor_t::disasm()
 334   uint64_t last_pc, last_bits, executions;
 335 };
 336
 337 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 338
 339 #define REGISTER_INSN(proc, name, match, mask) \
 340   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 341   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 342   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 343
 344 #endif