1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
12 #include "debug_rom_defines.h"
16 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
30 struct commit_log_reg_t
50 ACTION_DEBUG_EXCEPTION
= MCONTROL_ACTION_DEBUG_EXCEPTION
,
51 ACTION_DEBUG_MODE
= MCONTROL_ACTION_DEBUG_MODE
,
52 ACTION_TRACE_START
= MCONTROL_ACTION_TRACE_START
,
53 ACTION_TRACE_STOP
= MCONTROL_ACTION_TRACE_STOP
,
54 ACTION_TRACE_EMIT
= MCONTROL_ACTION_TRACE_EMIT
59 MATCH_EQUAL
= MCONTROL_MATCH_EQUAL
,
60 MATCH_NAPOT
= MCONTROL_MATCH_NAPOT
,
61 MATCH_GE
= MCONTROL_MATCH_GE
,
62 MATCH_LT
= MCONTROL_MATCH_LT
,
63 MATCH_MASK_LOW
= MCONTROL_MATCH_MASK_LOW
,
64 MATCH_MASK_HIGH
= MCONTROL_MATCH_MASK_HIGH
74 mcontrol_action_t action
;
76 mcontrol_match_t match
;
86 // architectural state of a RISC-V hart
91 static const int num_triggers
= 4;
94 regfile_t
<reg_t
, NXPR
, true> XPR
;
95 regfile_t
<freg_t
, NFPR
, false> FPR
;
97 // control and status registers
98 reg_t prv
; // TODO: Can this be an enum instead?
122 mcontrol_t mcontrol
[num_triggers
];
123 reg_t tdata2
[num_triggers
];
127 bool serialized
; // whether timer CSRs are in a well-defined state
129 // When true, execute a single instruction and then enter debug mode. This
130 // can only be set by executing dret.
137 reg_t load_reservation
;
139 #ifdef RISCV_ENABLE_COMMITLOG
140 commit_log_reg_t log_reg_write
;
141 reg_t last_inst_priv
;
151 } trigger_operation_t
;
153 // Count number of contiguous 1 bits starting from the LSB.
154 static int cto(reg_t val
)
157 while ((val
& 1) == 1)
162 // this class represents one processor in a RISC-V machine.
163 class processor_t
: public abstract_device_t
166 processor_t(const char* isa
, simif_t
* sim
, uint32_t id
, bool halt_on_reset
=false);
169 void set_debug(bool value
);
170 void set_histogram(bool value
);
172 void step(size_t n
); // run for n cycles
173 void set_csr(int which
, reg_t val
);
174 reg_t
get_csr(int which
);
175 mmu_t
* get_mmu() { return mmu
; }
176 state_t
* get_state() { return &state
; }
177 unsigned get_xlen() { return xlen
; }
178 unsigned get_max_xlen() { return max_xlen
; }
179 std::string
get_isa_string() { return isa_string
; }
180 unsigned get_flen() {
181 return supports_extension('Q') ? 128 :
182 supports_extension('D') ? 64 :
183 supports_extension('F') ? 32 : 0;
185 extension_t
* get_extension() { return ext
; }
186 bool supports_extension(unsigned char ext
) {
187 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
188 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
190 void check_pc_alignment(reg_t pc
) {
191 if (unlikely(pc
& 2) && !supports_extension('C'))
192 throw trap_instruction_address_misaligned(pc
);
194 reg_t
legalize_privilege(reg_t
);
195 void set_privilege(reg_t
);
196 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
197 void update_histogram(reg_t pc
);
198 const disassembler_t
* get_disassembler() { return disassembler
; }
200 void register_insn(insn_desc_t
);
201 void register_extension(extension_t
*);
203 // MMIO slave interface
204 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
205 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
207 // When true, display disassembly of each instruction that's executed.
209 // When true, take the slow simulation path.
211 bool halted() { return state
.dcsr
.cause
? true : false; }
214 // Return the index of a trigger that matched, or -1.
215 inline int trigger_match(trigger_operation_t operation
, reg_t address
, reg_t data
)
217 if (state
.dcsr
.cause
)
220 bool chain_ok
= true;
222 for (unsigned int i
= 0; i
< state
.num_triggers
; i
++) {
224 chain_ok
|= !state
.mcontrol
[i
].chain
;
228 if ((operation
== OPERATION_EXECUTE
&& !state
.mcontrol
[i
].execute
) ||
229 (operation
== OPERATION_STORE
&& !state
.mcontrol
[i
].store
) ||
230 (operation
== OPERATION_LOAD
&& !state
.mcontrol
[i
].load
) ||
231 (state
.prv
== PRV_M
&& !state
.mcontrol
[i
].m
) ||
232 (state
.prv
== PRV_S
&& !state
.mcontrol
[i
].s
) ||
233 (state
.prv
== PRV_U
&& !state
.mcontrol
[i
].u
)) {
238 if (state
.mcontrol
[i
].select
) {
244 // We need this because in 32-bit mode sometimes the PC bits get sign
250 switch (state
.mcontrol
[i
].match
) {
252 if (value
!= state
.tdata2
[i
])
257 reg_t mask
= ~((1 << cto(state
.tdata2
[i
])) - 1);
258 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
263 if (value
< state
.tdata2
[i
])
267 if (value
>= state
.tdata2
[i
])
272 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
273 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
277 case MATCH_MASK_HIGH
:
279 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
280 if (((value
>> (xlen
/2)) & mask
) != (state
.tdata2
[i
] & mask
))
286 if (!state
.mcontrol
[i
].chain
) {
294 void trigger_updated();
298 mmu_t
* mmu
; // main memory is always accessed via the mmu
300 disassembler_t
* disassembler
;
307 std::string isa_string
;
308 bool histogram_enabled
;
311 std::vector
<insn_desc_t
> instructions
;
312 std::map
<reg_t
,uint64_t> pc_histogram
;
314 static const size_t OPCODE_CACHE_SIZE
= 8191;
315 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
317 void take_pending_interrupt() { take_interrupt(state
.mip
& state
.mie
); }
318 void take_interrupt(reg_t mask
); // take first enabled interrupt in mask
319 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
320 void disasm(insn_t insn
); // disassemble and print an instruction
323 void enter_debug_mode(uint8_t cause
);
326 friend class clint_t
;
327 friend class extension_t
;
329 void parse_isa_string(const char* isa
);
330 void build_opcode_map();
331 void register_base_instructions();
332 insn_func_t
decode_insn(insn_t insn
);
334 // Track repeated executions for processor_t::disasm()
335 uint64_t last_pc
, last_bits
, executions
;
338 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
340 #define REGISTER_INSN(proc, name, match, mask) \
341 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
342 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
343 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});