riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11 #include "debug_rom/debug_rom_defines.h"
  12
  13 class processor_t;
  14 class mmu_t;
  15 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  16 class sim_t;
  17 class trap_t;
  18 class extension_t;
  19 class disassembler_t;
  20
  21 struct insn_desc_t
  22 {
  23   insn_bits_t match;
  24   insn_bits_t mask;
  25   insn_func_t rv32;
  26   insn_func_t rv64;
  27 };
  28
  29 struct commit_log_reg_t
  30 {
  31   reg_t addr;
  32   reg_t data;
  33 };
  34
  35 typedef struct
  36 {
  37   uint8_t prv;
  38   bool step;
  39   bool ebreakm;
  40   bool ebreakh;
  41   bool ebreaks;
  42   bool ebreaku;
  43   bool halt;
  44   uint8_t cause;
  45 } dcsr_t;
  46
  47 typedef enum
  48 {
  49   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
  50   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
  51   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
  52   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
  53   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
  54 } mcontrol_action_t;
  55
  56 typedef enum
  57 {
  58   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
  59   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
  60   MATCH_GE = MCONTROL_MATCH_GE,
  61   MATCH_LT = MCONTROL_MATCH_LT,
  62   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
  63   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
  64 } mcontrol_match_t;
  65
  66 typedef struct
  67 {
  68   uint8_t type;
  69   bool dmode;
  70   uint8_t maskmax;
  71   bool select;
  72   bool timing;
  73   mcontrol_action_t action;
  74   bool chain;
  75   mcontrol_match_t match;
  76   bool m;
  77   bool h;
  78   bool s;
  79   bool u;
  80   bool execute;
  81   bool store;
  82   bool load;
  83 } mcontrol_t;
  84
  85 // architectural state of a RISC-V hart
  86 struct state_t
  87 {
  88   void reset();
  89
  90   static const int num_triggers = 4;
  91
  92   reg_t pc;
  93   regfile_t<reg_t, NXPR, true> XPR;
  94   regfile_t<freg_t, NFPR, false> FPR;
  95
  96   // control and status registers
  97   reg_t prv;    // TODO: Can this be an enum instead?
  98   reg_t mstatus;
  99   reg_t mepc;
 100   reg_t mbadaddr;
 101   reg_t mscratch;
 102   reg_t mtvec;
 103   reg_t mcause;
 104   reg_t minstret;
 105   reg_t mie;
 106   reg_t mip;
 107   reg_t medeleg;
 108   reg_t mideleg;
 109   uint32_t mcounteren;
 110   uint32_t scounteren;
 111   reg_t sepc;
 112   reg_t sbadaddr;
 113   reg_t sscratch;
 114   reg_t stvec;
 115   reg_t sptbr;
 116   reg_t scause;
 117   reg_t dpc;
 118   reg_t dscratch;
 119   dcsr_t dcsr;
 120   reg_t tselect;
 121   mcontrol_t mcontrol[num_triggers];
 122   reg_t tdata2[num_triggers];
 123
 124   uint32_t fflags;
 125   uint32_t frm;
 126   bool serialized; // whether timer CSRs are in a well-defined state
 127
 128   // When true, execute a single instruction and then enter debug mode.  This
 129   // can only be set by executing dret.
 130   enum {
 131       STEP_NONE,
 132       STEP_STEPPING,
 133       STEP_STEPPED
 134   } single_step;
 135
 136   reg_t load_reservation;
 137
 138 #ifdef RISCV_ENABLE_COMMITLOG
 139   commit_log_reg_t log_reg_write;
 140   reg_t last_inst_priv;
 141 #endif
 142 };
 143
 144 typedef enum {
 145   OPERATION_EXECUTE,
 146   OPERATION_STORE,
 147   OPERATION_LOAD,
 148 } trigger_operation_t;
 149
 150 // Count number of contiguous 1 bits starting from the LSB.
 151 static int cto(reg_t val)
 152 {
 153   int res = 0;
 154   while ((val & 1) == 1)
 155     val >>= 1, res++;
 156   return res;
 157 }
 158
 159 // this class represents one processor in a RISC-V machine.
 160 class processor_t : public abstract_device_t
 161 {
 162 public:
 163   processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
 164   ~processor_t();
 165
 166   void set_debug(bool value);
 167   void set_histogram(bool value);
 168   void reset();
 169   void step(size_t n); // run for n cycles
 170   void set_csr(int which, reg_t val);
 171   reg_t get_csr(int which);
 172   mmu_t* get_mmu() { return mmu; }
 173   state_t* get_state() { return &state; }
 174   extension_t* get_extension() { return ext; }
 175   bool supports_extension(unsigned char ext) {
 176     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 177     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 178   }
 179   void set_privilege(reg_t);
 180   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 181   void update_histogram(reg_t pc);
 182   const disassembler_t* get_disassembler() { return disassembler; }
 183
 184   void register_insn(insn_desc_t);
 185   void register_extension(extension_t*);
 186
 187   // MMIO slave interface
 188   bool load(reg_t addr, size_t len, uint8_t* bytes);
 189   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 190
 191   // When true, display disassembly of each instruction that's executed.
 192   bool debug;
 193   // When true, take the slow simulation path.
 194   bool slow_path();
 195   bool halted() { return state.dcsr.cause ? true : false; }
 196   bool halt_request;
 197
 198   // Return the index of a trigger that matched, or -1.
 199   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
 200   {
 201     if (state.dcsr.cause)
 202       return -1;
 203
 204     bool chain_ok = true;
 205
 206     for (unsigned int i = 0; i < state.num_triggers; i++) {
 207       if (!chain_ok) {
 208         chain_ok |= !state.mcontrol[i].chain;
 209         continue;
 210       }
 211
 212       if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
 213           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
 214           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
 215           (state.prv == PRV_M && !state.mcontrol[i].m) ||
 216           (state.prv == PRV_H && !state.mcontrol[i].h) ||
 217           (state.prv == PRV_S && !state.mcontrol[i].s) ||
 218           (state.prv == PRV_U && !state.mcontrol[i].u)) {
 219         continue;
 220       }
 221
 222       reg_t value;
 223       if (state.mcontrol[i].select) {
 224         value = data;
 225       } else {
 226         value = address;
 227       }
 228
 229       // We need this because in 32-bit mode sometimes the PC bits get sign
 230       // extended.
 231       if (xlen == 32) {
 232         value &= 0xffffffff;
 233       }
 234
 235       switch (state.mcontrol[i].match) {
 236         case MATCH_EQUAL:
 237           if (value != state.tdata2[i])
 238             continue;
 239           break;
 240         case MATCH_NAPOT:
 241           {
 242             reg_t mask = ~((1 << cto(state.tdata2[i])) - 1);
 243             if ((value & mask) != (state.tdata2[i] & mask))
 244               continue;
 245           }
 246           break;
 247         case MATCH_GE:
 248           if (value < state.tdata2[i])
 249             continue;
 250           break;
 251         case MATCH_LT:
 252           if (value >= state.tdata2[i])
 253             continue;
 254           break;
 255         case MATCH_MASK_LOW:
 256           {
 257             reg_t mask = state.tdata2[i] >> (xlen/2);
 258             if ((value & mask) != (state.tdata2[i] & mask))
 259               continue;
 260           }
 261           break;
 262         case MATCH_MASK_HIGH:
 263           {
 264             reg_t mask = state.tdata2[i] >> (xlen/2);
 265             if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask))
 266               continue;
 267           }
 268           break;
 269       }
 270
 271       if (!state.mcontrol[i].chain) {
 272         return i;
 273       }
 274       chain_ok = true;
 275     }
 276     return -1;
 277   }
 278
 279   void trigger_updated();
 280
 281 private:
 282   sim_t* sim;
 283   mmu_t* mmu; // main memory is always accessed via the mmu
 284   extension_t* ext;
 285   disassembler_t* disassembler;
 286   state_t state;
 287   uint32_t id;
 288   unsigned max_xlen;
 289   unsigned xlen;
 290   reg_t isa;
 291   reg_t max_isa;
 292   std::string isa_string;
 293   bool histogram_enabled;
 294   bool halt_on_reset;
 295
 296   std::vector<insn_desc_t> instructions;
 297   std::map<reg_t,uint64_t> pc_histogram;
 298
 299   static const size_t OPCODE_CACHE_SIZE = 8191;
 300   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 301
 302   void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
 303   void take_interrupt(reg_t mask); // take first enabled interrupt in mask
 304   void take_trap(trap_t& t, reg_t epc); // take an exception
 305   void disasm(insn_t insn); // disassemble and print an instruction
 306   int paddr_bits();
 307
 308   void enter_debug_mode(uint8_t cause);
 309
 310   friend class sim_t;
 311   friend class mmu_t;
 312   friend class clint_t;
 313   friend class extension_t;
 314
 315   void parse_isa_string(const char* isa);
 316   void build_opcode_map();
 317   void register_base_instructions();
 318   insn_func_t decode_insn(insn_t insn);
 319 };
 320
 321 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 322
 323 #define REGISTER_INSN(proc, name, match, mask) \
 324   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 325   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 326   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 327
 328 #endif