riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include "trap.h"
   9 #include <string>
  10 #include <vector>
  11 #include <map>
  12 #include "debug_rom_defines.h"
  13
  14 class processor_t;
  15 class mmu_t;
  16 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  17 class simif_t;
  18 class trap_t;
  19 class extension_t;
  20 class disassembler_t;
  21
  22 struct insn_desc_t
  23 {
  24   insn_bits_t match;
  25   insn_bits_t mask;
  26   insn_func_t rv32;
  27   insn_func_t rv64;
  28 };
  29
  30 struct commit_log_reg_t
  31 {
  32   reg_t addr;
  33   freg_t data;
  34 };
  35
  36 typedef struct
  37 {
  38   uint8_t prv;
  39   bool step;
  40   bool ebreakm;
  41   bool ebreakh;
  42   bool ebreaks;
  43   bool ebreaku;
  44   bool halt;
  45   uint8_t cause;
  46 } dcsr_t;
  47
  48 typedef enum
  49 {
  50   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
  51   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
  52   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
  53   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
  54   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
  55 } mcontrol_action_t;
  56
  57 typedef enum
  58 {
  59   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
  60   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
  61   MATCH_GE = MCONTROL_MATCH_GE,
  62   MATCH_LT = MCONTROL_MATCH_LT,
  63   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
  64   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
  65 } mcontrol_match_t;
  66
  67 typedef struct
  68 {
  69   uint8_t type;
  70   bool dmode;
  71   uint8_t maskmax;
  72   bool select;
  73   bool timing;
  74   mcontrol_action_t action;
  75   bool chain;
  76   mcontrol_match_t match;
  77   bool m;
  78   bool h;
  79   bool s;
  80   bool u;
  81   bool execute;
  82   bool store;
  83   bool load;
  84 } mcontrol_t;
  85
  86 // architectural state of a RISC-V hart
  87 struct state_t
  88 {
  89   void reset(reg_t max_isa);
  90
  91   static const int num_triggers = 4;
  92
  93   reg_t pc;
  94   regfile_t<reg_t, NXPR, true> XPR;
  95   regfile_t<freg_t, NFPR, false> FPR;
  96
  97   // control and status registers
  98   reg_t prv;    // TODO: Can this be an enum instead?
  99   reg_t misa;
 100   reg_t mstatus;
 101   reg_t mepc;
 102   reg_t mtval;
 103   reg_t mscratch;
 104   reg_t mtvec;
 105   reg_t mcause;
 106   reg_t minstret;
 107   reg_t mie;
 108   reg_t mip;
 109   reg_t medeleg;
 110   reg_t mideleg;
 111   uint32_t mcounteren;
 112   uint32_t scounteren;
 113   reg_t sepc;
 114   reg_t stval;
 115   reg_t sscratch;
 116   reg_t stvec;
 117   reg_t satp;
 118   reg_t scause;
 119   reg_t dpc;
 120   reg_t dscratch;
 121   dcsr_t dcsr;
 122   reg_t tselect;
 123   mcontrol_t mcontrol[num_triggers];
 124   reg_t tdata2[num_triggers];
 125
 126   uint32_t fflags;
 127   uint32_t frm;
 128   bool serialized; // whether timer CSRs are in a well-defined state
 129
 130   // When true, execute a single instruction and then enter debug mode.  This
 131   // can only be set by executing dret.
 132   enum {
 133       STEP_NONE,
 134       STEP_STEPPING,
 135       STEP_STEPPED
 136   } single_step;
 137
 138   reg_t load_reservation;
 139
 140 #ifdef RISCV_ENABLE_COMMITLOG
 141   commit_log_reg_t log_reg_write;
 142   reg_t last_inst_priv;
 143   int last_inst_xlen;
 144   int last_inst_flen;
 145 #endif
 146 };
 147
 148 typedef enum {
 149   OPERATION_EXECUTE,
 150   OPERATION_STORE,
 151   OPERATION_LOAD,
 152 } trigger_operation_t;
 153
 154 // Count number of contiguous 1 bits starting from the LSB.
 155 static int cto(reg_t val)
 156 {
 157   int res = 0;
 158   while ((val & 1) == 1)
 159     val >>= 1, res++;
 160   return res;
 161 }
 162
 163 // this class represents one processor in a RISC-V machine.
 164 class processor_t : public abstract_device_t
 165 {
 166 public:
 167   processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset=false);
 168   ~processor_t();
 169
 170   void set_debug(bool value);
 171   void set_histogram(bool value);
 172   void reset();
 173   void step(size_t n); // run for n cycles
 174   void set_csr(int which, reg_t val);
 175   reg_t get_csr(int which);
 176   mmu_t* get_mmu() { return mmu; }
 177   state_t* get_state() { return &state; }
 178   unsigned get_xlen() { return xlen; }
 179   unsigned get_max_xlen() { return max_xlen; }
 180   std::string get_isa_string() { return isa_string; }
 181   unsigned get_flen() {
 182     return supports_extension('Q') ? 128 :
 183            supports_extension('D') ? 64 :
 184            supports_extension('F') ? 32 : 0;
 185   }
 186   extension_t* get_extension() { return ext; }
 187   bool supports_extension(unsigned char ext) {
 188     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 189     return ext >= 'A' && ext <= 'Z' && ((state.misa >> (ext - 'A')) & 1);
 190   }
 191   void check_pc_alignment(reg_t pc) {
 192     if (unlikely(pc & 2) && !supports_extension('C'))
 193       throw trap_instruction_address_misaligned(pc);
 194   }
 195   reg_t legalize_privilege(reg_t);
 196   void set_privilege(reg_t);
 197   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 198   void update_histogram(reg_t pc);
 199   const disassembler_t* get_disassembler() { return disassembler; }
 200
 201   void register_insn(insn_desc_t);
 202   void register_extension(extension_t*);
 203
 204   // MMIO slave interface
 205   bool load(reg_t addr, size_t len, uint8_t* bytes);
 206   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 207
 208   // When true, display disassembly of each instruction that's executed.
 209   bool debug;
 210   // When true, take the slow simulation path.
 211   bool slow_path();
 212   bool halted() { return state.dcsr.cause ? true : false; }
 213   bool halt_request;
 214
 215   // Return the index of a trigger that matched, or -1.
 216   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
 217   {
 218     if (state.dcsr.cause)
 219       return -1;
 220
 221     bool chain_ok = true;
 222
 223     for (unsigned int i = 0; i < state.num_triggers; i++) {
 224       if (!chain_ok) {
 225         chain_ok |= !state.mcontrol[i].chain;
 226         continue;
 227       }
 228
 229       if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
 230           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
 231           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
 232           (state.prv == PRV_M && !state.mcontrol[i].m) ||
 233           (state.prv == PRV_S && !state.mcontrol[i].s) ||
 234           (state.prv == PRV_U && !state.mcontrol[i].u)) {
 235         continue;
 236       }
 237
 238       reg_t value;
 239       if (state.mcontrol[i].select) {
 240         value = data;
 241       } else {
 242         value = address;
 243       }
 244
 245       // We need this because in 32-bit mode sometimes the PC bits get sign
 246       // extended.
 247       if (xlen == 32) {
 248         value &= 0xffffffff;
 249       }
 250
 251       switch (state.mcontrol[i].match) {
 252         case MATCH_EQUAL:
 253           if (value != state.tdata2[i])
 254             continue;
 255           break;
 256         case MATCH_NAPOT:
 257           {
 258             reg_t mask = ~((1 << cto(state.tdata2[i])) - 1);
 259             if ((value & mask) != (state.tdata2[i] & mask))
 260               continue;
 261           }
 262           break;
 263         case MATCH_GE:
 264           if (value < state.tdata2[i])
 265             continue;
 266           break;
 267         case MATCH_LT:
 268           if (value >= state.tdata2[i])
 269             continue;
 270           break;
 271         case MATCH_MASK_LOW:
 272           {
 273             reg_t mask = state.tdata2[i] >> (xlen/2);
 274             if ((value & mask) != (state.tdata2[i] & mask))
 275               continue;
 276           }
 277           break;
 278         case MATCH_MASK_HIGH:
 279           {
 280             reg_t mask = state.tdata2[i] >> (xlen/2);
 281             if (((value >> (xlen/2)) & mask) != (state.tdata2[i] & mask))
 282               continue;
 283           }
 284           break;
 285       }
 286
 287       if (!state.mcontrol[i].chain) {
 288         return i;
 289       }
 290       chain_ok = true;
 291     }
 292     return -1;
 293   }
 294
 295   void trigger_updated();
 296
 297 private:
 298   simif_t* sim;
 299   mmu_t* mmu; // main memory is always accessed via the mmu
 300   extension_t* ext;
 301   disassembler_t* disassembler;
 302   state_t state;
 303   uint32_t id;
 304   unsigned max_xlen;
 305   unsigned xlen;
 306   reg_t max_isa;
 307   std::string isa_string;
 308   bool histogram_enabled;
 309   bool halt_on_reset;
 310
 311   std::vector<insn_desc_t> instructions;
 312   std::map<reg_t,uint64_t> pc_histogram;
 313
 314   static const size_t OPCODE_CACHE_SIZE = 8191;
 315   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 316
 317   void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
 318   void take_interrupt(reg_t mask); // take first enabled interrupt in mask
 319   void take_trap(trap_t& t, reg_t epc); // take an exception
 320   void disasm(insn_t insn); // disassemble and print an instruction
 321   int paddr_bits();
 322
 323   void enter_debug_mode(uint8_t cause);
 324
 325   friend class mmu_t;
 326   friend class clint_t;
 327   friend class extension_t;
 328
 329   void parse_isa_string(const char* isa);
 330   void build_opcode_map();
 331   void register_base_instructions();
 332   insn_func_t decode_insn(insn_t insn);
 333
 334   // Track repeated executions for processor_t::disasm()
 335   uint64_t last_pc, last_bits, executions;
 336 };
 337
 338 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 339
 340 #define REGISTER_INSN(proc, name, match, mask) \
 341   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 342   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 343   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 344
 345 #endif