riscv/processor.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_PROCESSOR_H
   4 #define _RISCV_PROCESSOR_H
   5
   6 #include "decode.h"
   7 #include <cstring>
   8 #include "config.h"
   9 #include <map>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16
  17 // architectural state of a RISC-V hart
  18 struct state_t
  19 {
  20   void reset();
  21
  22   // user-visible state
  23   reg_t pc;
  24   regfile_t<reg_t, NXPR, true> XPR;
  25   regfile_t<freg_t, NFPR, false> FPR;
  26   reg_t cycle;
  27
  28   // privileged control registers
  29   reg_t epc;
  30   reg_t badvaddr;
  31   reg_t evec;
  32   reg_t ptbr;
  33   reg_t pcr_k0;
  34   reg_t pcr_k1;
  35   reg_t cause;
  36   reg_t tohost;
  37   reg_t fromhost;
  38   uint32_t sr; // only modify the status register using set_pcr()
  39   uint32_t fsr;
  40   uint32_t count;
  41   uint32_t compare;
  42
  43   reg_t load_reservation;
  44 };
  45
  46 // this class represents one processor in a RISC-V machine.
  47 class processor_t
  48 {
  49 public:
  50   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  51   ~processor_t();
  52
  53   void reset(bool value);
  54   void step(size_t n, bool noisy); // run for n cycles
  55   void deliver_ipi(); // register an interprocessor interrupt
  56   bool running() { return run; }
  57   reg_t set_pcr(int which, reg_t val);
  58   uint32_t set_fsr(uint32_t val); // set the floating-point status register
  59   void set_interrupt(int which, bool on);
  60   reg_t get_pcr(int which);
  61   uint32_t get_fsr() { return state.fsr; }
  62   mmu_t* get_mmu() { return &mmu; }
  63   state_t* get_state() { return &state; }
  64   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  65
  66   void register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64);
  67
  68 private:
  69   sim_t& sim;
  70   mmu_t& mmu; // main memory is always accessed via the mmu
  71   state_t state;
  72   uint32_t id;
  73   bool run; // !reset
  74
  75   struct opcode_map_entry_t
  76   {
  77     uint32_t match;
  78     uint32_t mask;
  79     insn_func_t rv32;
  80     insn_func_t rv64;
  81   };
  82   unsigned opcode_bits;
  83   std::multimap<uint32_t, opcode_map_entry_t> opcode_map;
  84
  85   void take_interrupt(); // take a trap if any interrupts are pending
  86   void take_trap(reg_t pc, trap_t& t, bool noisy); // take an exception
  87   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
  88
  89   friend class sim_t;
  90   friend class mmu_t;
  91   friend class htif_isasim_t;
  92
  93   insn_func_t decode_insn(insn_t insn);
  94 };
  95
  96 #endif