riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "mmu.h"
   8 #include "icsim.h"
   9
  10 #define MAX_UTS 2048
  11
  12 class processor_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15
  16 class processor_t
  17 {
  18 public:
  19   processor_t(sim_t* _sim, mmu_t* _mmu);
  20   ~processor_t();
  21   void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
  22   void step(size_t n, bool noisy);
  23   void deliver_ipi();
  24
  25 private:
  26   sim_t* sim;
  27
  28   // architected state
  29   reg_t XPR[NXPR];
  30   freg_t FPR[NFPR];
  31
  32   // privileged control registers
  33   reg_t pc;
  34   reg_t epc;
  35   reg_t badvaddr;
  36   reg_t cause;
  37   reg_t evec;
  38   reg_t tohost;
  39   reg_t fromhost;
  40   reg_t pcr_k0;
  41   reg_t pcr_k1;
  42   uint32_t id;
  43   uint32_t sr;
  44   uint32_t count;
  45   uint32_t compare;
  46
  47   bool run;
  48
  49   // unprivileged control registers
  50   uint32_t fsr;
  51
  52   // # of bits in an XPR (32 or 64). (redundant with sr)
  53   int xprlen;
  54
  55   // shared memory
  56   mmu_t& mmu;
  57
  58   // counters
  59   reg_t cycle;
  60
  61   // functions
  62   void reset();
  63   void take_interrupt();
  64   void set_sr(uint32_t val);
  65   void set_fsr(uint32_t val);
  66   void take_trap(trap_t t, bool noisy);
  67   void disasm(insn_t insn, reg_t pc);
  68
  69   // vector stuff
  70   void vcfg();
  71   void setvl(int vlapp);
  72
  73   reg_t vecbanks;
  74   uint32_t vecbanks_count;
  75
  76   bool utmode;
  77   int utidx;
  78   int vlmax;
  79   int vl;
  80   int nxfpr_bank;
  81   int nxpr_use;
  82   int nfpr_use;
  83   processor_t* uts[MAX_UTS];
  84
  85   // cache sim
  86   icsim_t* icsim;
  87   icsim_t* dcsim;
  88   icsim_t* itlbsim;
  89   icsim_t* dtlbsim;
  90
  91   friend class sim_t;
  92
  93   #include "dispatch.h"
  94 };
  95
  96 #endif