riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include <cstring>
   8 #include <vector>
   9 #include <map>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16 class extension_t;
  17 class disassembler_t;
  18
  19 struct insn_desc_t
  20 {
  21   uint32_t match;
  22   uint32_t mask;
  23   insn_func_t rv32;
  24   insn_func_t rv64;
  25 };
  26
  27 struct commit_log_reg_t
  28 {
  29   reg_t addr;
  30   reg_t data;
  31 };
  32
  33 // architectural state of a RISC-V hart
  34 struct state_t
  35 {
  36   void reset();
  37
  38   reg_t pc;
  39   regfile_t<reg_t, NXPR, true> XPR;
  40   regfile_t<freg_t, NFPR, false> FPR;
  41
  42   // control and status registers
  43   reg_t mstatus;
  44   reg_t mepc;
  45   reg_t mbadaddr;
  46   reg_t mscratch;
  47   reg_t mcause;
  48   reg_t mtime;
  49   reg_t mie;
  50   reg_t mip;
  51   reg_t sepc;
  52   reg_t sbadaddr;
  53   reg_t sscratch;
  54   reg_t stvec;
  55   reg_t sptbr;
  56   reg_t scause;
  57   reg_t sutime_delta;
  58   reg_t tohost;
  59   reg_t fromhost;
  60   bool serialized; // whether timer CSRs are in a well-defined state
  61   uint32_t stimecmp;
  62   uint32_t fflags;
  63   uint32_t frm;
  64
  65   reg_t load_reservation;
  66
  67 #ifdef RISCV_ENABLE_COMMITLOG
  68   commit_log_reg_t log_reg_write;
  69 #endif
  70 };
  71
  72 // this class represents one processor in a RISC-V machine.
  73 class processor_t
  74 {
  75 public:
  76   processor_t(const char* isa, sim_t* sim, uint32_t id);
  77   ~processor_t();
  78
  79   void set_debug(bool value);
  80   void set_histogram(bool value);
  81   void reset(bool value);
  82   void step(size_t n); // run for n cycles
  83   void deliver_ipi(); // register an interprocessor interrupt
  84   bool running() { return run; }
  85   void set_csr(int which, reg_t val);
  86   void raise_interrupt(reg_t which);
  87   reg_t get_csr(int which);
  88   mmu_t* get_mmu() { return mmu; }
  89   state_t* get_state() { return &state; }
  90   extension_t* get_extension() { return ext; }
  91   bool supports_extension(unsigned char ext) {
  92     return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
  93   }
  94   void push_privilege_stack();
  95   void pop_privilege_stack();
  96   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  97   void update_histogram(size_t pc);
  98
  99   void register_insn(insn_desc_t);
 100   void register_extension(extension_t*);
 101
 102 private:
 103   sim_t* sim;
 104   mmu_t* mmu; // main memory is always accessed via the mmu
 105   extension_t* ext;
 106   disassembler_t* disassembler;
 107   state_t state;
 108   reg_t cpuid;
 109   uint32_t id;
 110   int max_xlen;
 111   int xlen;
 112   bool run; // !reset
 113   bool debug;
 114   bool histogram_enabled;
 115
 116   std::vector<insn_desc_t> instructions;
 117   std::vector<insn_desc_t*> opcode_map;
 118   std::vector<insn_desc_t> opcode_store;
 119   std::map<size_t,size_t> pc_histogram;
 120
 121   void take_interrupt(); // take a trap if any interrupts are pending
 122   void take_trap(trap_t& t, reg_t epc); // take an exception
 123   void disasm(insn_t insn); // disassemble and print an instruction
 124
 125   friend class sim_t;
 126   friend class mmu_t;
 127   friend class extension_t;
 128
 129   void parse_isa_string(const char* isa);
 130   void build_opcode_map();
 131   insn_func_t decode_insn(insn_t insn);
 132 };
 133
 134 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 135
 136 #define REGISTER_INSN(proc, name, match, mask) \
 137   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 138   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 139   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 140
 141 #endif