riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include <cstring>
   8 #include <memory>
   9 #include <vector>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16 class extension_t;
  17 class disassembler_t;
  18
  19 struct insn_desc_t
  20 {
  21   uint32_t match;
  22   uint32_t mask;
  23   insn_func_t rv32;
  24   insn_func_t rv64;
  25 };
  26
  27 // architectural state of a RISC-V hart
  28 struct state_t
  29 {
  30   void reset();
  31
  32   reg_t pc;
  33   regfile_t<reg_t, NXPR, true> XPR;
  34   regfile_t<freg_t, NFPR, false> FPR;
  35
  36   // control and status registers
  37   reg_t epc;
  38   reg_t badvaddr;
  39   reg_t evec;
  40   reg_t ptbr;
  41   reg_t pcr_k0;
  42   reg_t pcr_k1;
  43   reg_t cause;
  44   reg_t tohost;
  45   reg_t fromhost;
  46   reg_t count;
  47   uint32_t compare;
  48   uint32_t sr; // only modify the status register using set_pcr()
  49   uint32_t fflags;
  50   uint32_t frm;
  51
  52   reg_t load_reservation;
  53 };
  54
  55 // this class represents one processor in a RISC-V machine.
  56 class processor_t
  57 {
  58 public:
  59   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  60   ~processor_t();
  61
  62   void set_debug(bool value);
  63   void reset(bool value);
  64   void step(size_t n); // run for n cycles
  65   void deliver_ipi(); // register an interprocessor interrupt
  66   bool running() { return run; }
  67   reg_t set_pcr(int which, reg_t val);
  68   void set_fromhost(reg_t val);
  69   void set_interrupt(int which, bool on);
  70   reg_t get_pcr(int which);
  71   mmu_t* get_mmu() { return mmu; }
  72   state_t* get_state() { return &state; }
  73   extension_t* get_extension() { return ext; }
  74   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  75
  76   void register_insn(insn_desc_t);
  77   void register_extension(extension_t*);
  78
  79 private:
  80   sim_t* sim;
  81   mmu_t* mmu; // main memory is always accessed via the mmu
  82   extension_t* ext;
  83   std::unique_ptr<disassembler_t> disassembler;
  84   state_t state;
  85   uint32_t id;
  86   bool run; // !reset
  87   bool debug;
  88   bool rv64;
  89
  90   std::vector<insn_desc_t> instructions;
  91   std::vector<insn_desc_t*> opcode_map;
  92   std::vector<insn_desc_t> opcode_store;
  93
  94   void take_interrupt(); // take a trap if any interrupts are pending
  95   void take_trap(trap_t& t); // take an exception
  96   void disasm(insn_t insn); // disassemble and print an instruction
  97
  98   friend class sim_t;
  99   friend class mmu_t;
 100   friend class extension_t;
 101
 102   void build_opcode_map();
 103   insn_func_t decode_insn(insn_t insn);
 104 };
 105
 106 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 107
 108 #define REGISTER_INSN(proc, name, match, mask) \
 109   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 110   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 111   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 112
 113 #endif