commit log now correctly prints privilege
[riscv-isa-sim.git] / riscv / processor.h
1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
4
5 #include "decode.h"
6 #include "config.h"
7 #include <cstring>
8 #include <vector>
9 #include <map>
10
11 class processor_t;
12 class mmu_t;
13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
14 class sim_t;
15 class trap_t;
16 class extension_t;
17 class disassembler_t;
18
19 struct insn_desc_t
20 {
21 insn_bits_t match;
22 insn_bits_t mask;
23 insn_func_t rv32;
24 insn_func_t rv64;
25 };
26
27 struct commit_log_reg_t
28 {
29 reg_t addr;
30 reg_t data;
31 };
32
33 // architectural state of a RISC-V hart
34 struct state_t
35 {
36 void reset();
37
38 reg_t pc;
39 regfile_t<reg_t, NXPR, true> XPR;
40 regfile_t<freg_t, NFPR, false> FPR;
41
42 // control and status registers
43 reg_t mstatus;
44 reg_t mepc;
45 reg_t mbadaddr;
46 reg_t mtimecmp;
47 reg_t mscratch;
48 reg_t mcause;
49 reg_t minstret;
50 reg_t mie;
51 reg_t mip;
52 reg_t sepc;
53 reg_t sbadaddr;
54 reg_t sscratch;
55 reg_t stvec;
56 reg_t sptbr;
57 reg_t scause;
58 reg_t sutime_delta;
59 reg_t suinstret_delta;
60 reg_t tohost;
61 reg_t fromhost;
62 uint32_t fflags;
63 uint32_t frm;
64 bool serialized; // whether timer CSRs are in a well-defined state
65
66 reg_t load_reservation;
67
68 #ifdef RISCV_ENABLE_COMMITLOG
69 commit_log_reg_t log_reg_write;
70 reg_t last_inst_priv;
71 #endif
72 };
73
74 // this class represents one processor in a RISC-V machine.
75 class processor_t
76 {
77 public:
78 processor_t(const char* isa, sim_t* sim, uint32_t id);
79 ~processor_t();
80
81 void set_debug(bool value);
82 void set_histogram(bool value);
83 void reset(bool value);
84 void step(size_t n); // run for n cycles
85 void deliver_ipi(); // register an interprocessor interrupt
86 bool running() { return run; }
87 void set_csr(int which, reg_t val);
88 void raise_interrupt(reg_t which);
89 reg_t get_csr(int which);
90 mmu_t* get_mmu() { return mmu; }
91 state_t* get_state() { return &state; }
92 extension_t* get_extension() { return ext; }
93 bool supports_extension(unsigned char ext) {
94 return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
95 }
96 void push_privilege_stack();
97 void pop_privilege_stack();
98 void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
99 void update_histogram(size_t pc);
100
101 void register_insn(insn_desc_t);
102 void register_extension(extension_t*);
103
104 private:
105 sim_t* sim;
106 mmu_t* mmu; // main memory is always accessed via the mmu
107 extension_t* ext;
108 disassembler_t* disassembler;
109 state_t state;
110 reg_t cpuid;
111 uint32_t id;
112 int max_xlen;
113 int xlen;
114 bool run; // !reset
115 bool debug;
116 bool histogram_enabled;
117
118 std::vector<insn_desc_t> instructions;
119 std::map<size_t,size_t> pc_histogram;
120
121 static const size_t OPCODE_CACHE_SIZE = 8191;
122 insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
123
124 void check_timer();
125 void take_interrupt(); // take a trap if any interrupts are pending
126 void take_trap(trap_t& t, reg_t epc); // take an exception
127 void disasm(insn_t insn); // disassemble and print an instruction
128
129 friend class sim_t;
130 friend class mmu_t;
131 friend class extension_t;
132
133 void parse_isa_string(const char* isa);
134 void build_opcode_map();
135 void register_base_instructions();
136 insn_func_t decode_insn(insn_t insn);
137 };
138
139 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
140
141 #define REGISTER_INSN(proc, name, match, mask) \
142 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
143 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
144 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
145
146 #endif