riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "disasm.h"
   7 #include <cstring>
   8 #include "config.h"
   9 #include <map>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16 class extension_t;
  17
  18 struct insn_desc_t
  19 {
  20   uint32_t match;
  21   uint32_t mask;
  22   insn_func_t rv32;
  23   insn_func_t rv64;
  24 };
  25
  26 // architectural state of a RISC-V hart
  27 struct state_t
  28 {
  29   void reset();
  30
  31   reg_t pc;
  32   regfile_t<reg_t, NXPR, true> XPR;
  33   regfile_t<freg_t, NFPR, false> FPR;
  34
  35   // control and status registers
  36   reg_t epc;
  37   reg_t badvaddr;
  38   reg_t evec;
  39   reg_t ptbr;
  40   reg_t pcr_k0;
  41   reg_t pcr_k1;
  42   reg_t cause;
  43   reg_t tohost;
  44   reg_t fromhost;
  45   reg_t count;
  46   uint32_t compare;
  47   uint32_t sr; // only modify the status register using set_pcr()
  48   uint32_t fflags;
  49   uint32_t frm;
  50
  51   reg_t load_reservation;
  52 };
  53
  54 // this class represents one processor in a RISC-V machine.
  55 class processor_t
  56 {
  57 public:
  58   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  59   ~processor_t();
  60
  61   void set_debug(bool value);
  62   void reset(bool value);
  63   void step(size_t n); // run for n cycles
  64   void deliver_ipi(); // register an interprocessor interrupt
  65   bool running() { return run; }
  66   reg_t set_pcr(int which, reg_t val);
  67   void set_interrupt(int which, bool on);
  68   reg_t get_pcr(int which);
  69   mmu_t* get_mmu() { return mmu; }
  70   state_t* get_state() { return &state; }
  71   extension_t* get_extension() { return ext; }
  72   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  73
  74   void register_insn(insn_desc_t);
  75   void register_extension(extension_t*);
  76
  77 private:
  78   sim_t* sim;
  79   mmu_t* mmu; // main memory is always accessed via the mmu
  80   extension_t* ext;
  81   disassembler_t disassembler;
  82   state_t state;
  83   uint32_t id;
  84   bool run; // !reset
  85   bool debug;
  86
  87   unsigned opcode_bits;
  88   std::multimap<uint32_t, insn_desc_t> opcode_map;
  89
  90   void take_interrupt(); // take a trap if any interrupts are pending
  91   void take_trap(reg_t pc, trap_t& t); // take an exception
  92   void disasm(insn_t insn); // disassemble and print an instruction
  93
  94   friend class sim_t;
  95   friend class mmu_t;
  96   friend class extension_t;
  97   friend class htif_isasim_t;
  98
  99   insn_func_t decode_insn(insn_t insn);
 100 };
 101
 102 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 103
 104 #define REGISTER_INSN(proc, name, match, mask) \
 105   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 106   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 107   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 108
 109 #endif