riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include <cstring>
   8 #include <vector>
   9 #include <map>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16 class extension_t;
  17 class disassembler_t;
  18
  19 struct insn_desc_t
  20 {
  21   uint32_t match;
  22   uint32_t mask;
  23   insn_func_t rv32;
  24   insn_func_t rv64;
  25 };
  26
  27 struct commit_log_reg_t
  28 {
  29   uint32_t addr;
  30   reg_t data;
  31 };
  32
  33 // architectural state of a RISC-V hart
  34 struct state_t
  35 {
  36   void reset();
  37
  38   reg_t pc;
  39   regfile_t<reg_t, NXPR, true> XPR;
  40   regfile_t<freg_t, NFPR, false> FPR;
  41
  42   // control and status registers
  43   reg_t epc;
  44   reg_t badvaddr;
  45   reg_t evec;
  46   reg_t ptbr;
  47   reg_t pcr_k0;
  48   reg_t pcr_k1;
  49   reg_t cause;
  50   reg_t tohost;
  51   reg_t fromhost;
  52   reg_t count;
  53   uint32_t compare;
  54   uint32_t sr; // only modify the status register using set_pcr()
  55   uint32_t fflags;
  56   uint32_t frm;
  57
  58   reg_t load_reservation;
  59
  60 #ifdef RISCV_ENABLE_COMMITLOG
  61   commit_log_reg_t log_reg_write;
  62 #endif
  63 };
  64
  65 // this class represents one processor in a RISC-V machine.
  66 class processor_t
  67 {
  68 public:
  69   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  70   ~processor_t();
  71
  72   void set_debug(bool value);
  73   void set_histogram(bool value);
  74   void reset(bool value);
  75   void step(size_t n); // run for n cycles
  76   void deliver_ipi(); // register an interprocessor interrupt
  77   bool running() { return run; }
  78   void set_pcr(int which, reg_t val);
  79   void set_fromhost(reg_t val);
  80   void set_interrupt(int which, bool on);
  81   reg_t get_pcr(int which);
  82   mmu_t* get_mmu() { return mmu; }
  83   state_t* get_state() { return &state; }
  84   extension_t* get_extension() { return ext; }
  85   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  86   void update_histogram(size_t pc);
  87
  88   void register_insn(insn_desc_t);
  89   void register_extension(extension_t*);
  90
  91 private:
  92   sim_t* sim;
  93   mmu_t* mmu; // main memory is always accessed via the mmu
  94   extension_t* ext;
  95   disassembler_t* disassembler;
  96   state_t state;
  97   uint32_t id;
  98   bool run; // !reset
  99   bool debug;
 100   bool histogram_enabled;
 101   bool rv64;
 102   bool serialized;
 103
 104   std::vector<insn_desc_t> instructions;
 105   std::vector<insn_desc_t*> opcode_map;
 106   std::vector<insn_desc_t> opcode_store;
 107   std::map<size_t,size_t> pc_histogram;
 108
 109   void take_interrupt(); // take a trap if any interrupts are pending
 110   void serialize(); // collapse into defined architectural state
 111   reg_t take_trap(trap_t& t, reg_t epc); // take an exception
 112   void disasm(insn_t insn); // disassemble and print an instruction
 113
 114   friend class sim_t;
 115   friend class mmu_t;
 116   friend class extension_t;
 117
 118   void build_opcode_map();
 119   insn_func_t decode_insn(insn_t insn);
 120 };
 121
 122 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 123
 124 #define REGISTER_INSN(proc, name, match, mask) \
 125   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 126   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 127   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 128
 129 #endif