riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "config.h"
   8
   9 #define MAX_UTS 2048
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15
  16 // this class represents one processor in a RISC-V machine.
  17 class processor_t
  18 {
  19 public:
  20   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  21   ~processor_t();
  22
  23   void reset(bool value);
  24   void step(size_t n, bool noisy); // run for n cycles
  25   void deliver_ipi(); // register an interprocessor interrupt
  26   bool running() { return run; }
  27   void set_pcr(int which, reg_t val);
  28   reg_t get_pcr(int which);
  29   mmu_t* get_mmu() { return &mmu; }
  30
  31 private:
  32   sim_t& sim;
  33   mmu_t& mmu; // main memory is always accessed via the mmu
  34
  35   // user-visible architected state
  36   regfile_t<reg_t, NXPR, true> XPR;
  37   regfile_t<freg_t, NFPR, false> FPR;
  38   reg_t pc;
  39
  40   // counters
  41   reg_t cycle;
  42
  43   // privileged control registers
  44   reg_t epc;
  45   reg_t badvaddr;
  46   reg_t evec;
  47   reg_t pcr_k0;
  48   reg_t pcr_k1;
  49   reg_t cause;
  50   reg_t tohost;
  51   reg_t fromhost;
  52   uint32_t interrupts_pending;
  53   uint32_t id;
  54   uint32_t sr; // only modify the status register using set_pcr()
  55   uint32_t fsr;
  56   uint32_t count;
  57   uint32_t compare;
  58
  59   // # of bits in an XPR (32 or 64). (redundant with sr)
  60   int xprlen;
  61
  62   bool run; // !reset
  63
  64   // functions
  65   void take_interrupt(); // take a trap if any interrupts are pending
  66   void set_fsr(uint32_t val); // set the floating-point status register
  67   void take_trap(reg_t t, bool noisy); // take an exception
  68   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
  69
  70   // vector stuff
  71   void vcfg();
  72   void setvl(int vlapp);
  73
  74   reg_t vecbanks;
  75   uint32_t vecbanks_count;
  76
  77   bool utmode;
  78   uint32_t utidx;
  79   int vlmax;
  80   int vl;
  81   int nxfpr_bank;
  82   int nxpr_use;
  83   int nfpr_use;
  84   processor_t* uts[MAX_UTS];
  85
  86   // this constructor is used for each of the uts
  87   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx);
  88
  89   friend class sim_t;
  90   friend class mmu_t;
  91   friend class htif_isasim_t;
  92
  93   #include "dispatch.h"
  94 };
  95
  96 #ifndef RISCV_ENABLE_RVC
  97 # define set_pc(x) \
  98   do { if((x) & (sizeof(insn_t)-1)) \
  99        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 100        npc = (x); \
 101      } while(0)
 102 #else
 103 # define set_pc(x) \
 104   do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
 105        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 106        npc = (x); \
 107      } while(0)
 108 #endif
 109
 110 #endif