riscv/processor.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_PROCESSOR_H
   4 #define _RISCV_PROCESSOR_H
   5
   6 #include "decode.h"
   7 #include <cstring>
   8 #include "trap.h"
   9 #include "config.h"
  10
  11 #define MAX_UTS 2048
  12
  13 class processor_t;
  14 class mmu_t;
  15 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  16 class sim_t;
  17
  18 // this class represents one processor in a RISC-V machine.
  19 class processor_t
  20 {
  21 public:
  22   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  23   ~processor_t();
  24
  25   void reset(bool value);
  26   void step(size_t n, bool noisy); // run for n cycles
  27   void deliver_ipi(); // register an interprocessor interrupt
  28   bool running() { return run; }
  29   void set_pcr(int which, reg_t val);
  30   void set_interrupt(int which, bool on);
  31   reg_t get_pcr(int which);
  32   mmu_t* get_mmu() { return &mmu; }
  33
  34 private:
  35   sim_t& sim;
  36   mmu_t& mmu; // main memory is always accessed via the mmu
  37
  38   // user-visible architected state
  39   regfile_t<reg_t, NXPR, true> XPR;
  40   regfile_t<freg_t, NFPR, false> FPR;
  41   reg_t pc;
  42   reg_t cycle;
  43
  44   // privileged control registers
  45   reg_t epc;
  46   reg_t badvaddr;
  47   reg_t evec;
  48   reg_t pcr_k0;
  49   reg_t pcr_k1;
  50   reg_t cause;
  51   reg_t tohost;
  52   reg_t fromhost;
  53   uint32_t id;
  54   uint32_t sr; // only modify the status register using set_pcr()
  55   uint32_t fsr;
  56   uint32_t count;
  57   uint32_t compare;
  58
  59   bool run; // !reset
  60
  61   // functions
  62   void take_interrupt(); // take a trap if any interrupts are pending
  63   void set_fsr(uint32_t val); // set the floating-point status register
  64   void take_trap(reg_t t, bool noisy); // take an exception
  65   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
  66
  67   // vector stuff
  68   void vcfg();
  69   void setvl(int vlapp);
  70
  71   reg_t vecbanks;
  72   uint32_t vecbanks_count;
  73
  74   bool utmode;
  75   uint32_t utidx;
  76   int vlmax;
  77   int vl;
  78   int nxfpr_bank;
  79   int nxpr_use;
  80   int nfpr_use;
  81   processor_t* uts[MAX_UTS];
  82
  83   // this constructor is used for each of the uts
  84   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx);
  85
  86   friend class sim_t;
  87   friend class mmu_t;
  88   friend class htif_isasim_t;
  89
  90   #include "dispatch.h"
  91 };
  92
  93 #ifndef RISCV_ENABLE_RVC
  94 # define set_pc(x) \
  95   do { if((x) & (sizeof(insn_t)-1)) \
  96        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
  97        npc = (x); \
  98      } while(0)
  99 #else
 100 # define set_pc(x) \
 101   do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
 102        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 103        npc = (x); \
 104      } while(0)
 105 #endif
 106
 107 #endif