riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "mmu.h"
   8 #include "icsim.h"
   9
  10 #define MAX_UTS 2048
  11
  12 class sim_t;
  13
  14 class processor_t
  15 {
  16 public:
  17   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
  18   ~processor_t();
  19   void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
  20   void step(size_t n, bool noisy);
  21
  22 private:
  23   sim_t* sim;
  24
  25   // architected state
  26   reg_t XPR[NXPR];
  27   freg_t FPR[NFPR];
  28
  29   // privileged control registers
  30   reg_t pc;
  31   reg_t epc;
  32   reg_t badvaddr;
  33   reg_t cause;
  34   reg_t evec;
  35   reg_t tohost;
  36   reg_t fromhost;
  37   reg_t pcr_k0;
  38   reg_t pcr_k1;
  39   uint32_t id;
  40   uint32_t sr;
  41   uint32_t count;
  42   uint32_t compare;
  43
  44   // unprivileged control registers
  45   uint32_t fsr;
  46
  47   // # of bits in an XPR (32 or 64). (redundant with sr)
  48   int xprlen;
  49
  50   // shared memory
  51   mmu_t mmu;
  52
  53   // counters
  54   reg_t cycle;
  55
  56   // functions
  57   void set_sr(uint32_t val);
  58   void set_fsr(uint32_t val);
  59   void take_trap(trap_t t, bool noisy);
  60   void disasm(insn_t insn, reg_t pc);
  61
  62   // vector stuff
  63   void vcfg();
  64   void setvl(int vlapp);
  65
  66   reg_t vecbanks;
  67   uint32_t vecbanks_count;
  68
  69   bool utmode;
  70   int utidx;
  71   int vlmax;
  72   int vl;
  73   int nxfpr_bank;
  74   int nxpr_use;
  75   int nfpr_use;
  76   processor_t* uts[MAX_UTS];
  77
  78   // cache sim
  79   icsim_t* icsim;
  80   icsim_t* dcsim;
  81   icsim_t* itlbsim;
  82   icsim_t* dtlbsim;
  83
  84   friend class sim_t;
  85 };
  86
  87 #endif