riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include <cstring>
   8 #include <vector>
   9 #include <map>
  10
  11 class processor_t;
  12 class mmu_t;
  13 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  14 class sim_t;
  15 class trap_t;
  16 class extension_t;
  17 class disassembler_t;
  18
  19 struct insn_desc_t
  20 {
  21   uint32_t match;
  22   uint32_t mask;
  23   insn_func_t rv32;
  24   insn_func_t rv64;
  25 };
  26
  27 struct commit_log_reg_t
  28 {
  29   reg_t addr;
  30   reg_t data;
  31 };
  32
  33 // architectural state of a RISC-V hart
  34 struct state_t
  35 {
  36   void reset();
  37
  38   reg_t pc;
  39   regfile_t<reg_t, NXPR, true> XPR;
  40   regfile_t<freg_t, NFPR, false> FPR;
  41
  42   // control and status registers
  43   reg_t mstatus;
  44   reg_t mepc;
  45   reg_t mbadaddr;
  46   reg_t mscratch;
  47   reg_t mcause;
  48   reg_t sepc;
  49   reg_t sbadaddr;
  50   reg_t sscratch;
  51   reg_t stvec;
  52   reg_t sptbr;
  53   reg_t scause;
  54   reg_t tohost;
  55   reg_t fromhost;
  56   reg_t scount;
  57   bool stip;
  58   uint32_t stimecmp;
  59   uint32_t fflags;
  60   uint32_t frm;
  61
  62   reg_t load_reservation;
  63
  64 #ifdef RISCV_ENABLE_COMMITLOG
  65   commit_log_reg_t log_reg_write;
  66 #endif
  67 };
  68
  69 // this class represents one processor in a RISC-V machine.
  70 class processor_t
  71 {
  72 public:
  73   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  74   ~processor_t();
  75
  76   void set_debug(bool value);
  77   void set_histogram(bool value);
  78   void reset(bool value);
  79   void step(size_t n); // run for n cycles
  80   void deliver_ipi(); // register an interprocessor interrupt
  81   bool running() { return run; }
  82   void set_csr(int which, reg_t val);
  83   void raise_interrupt(reg_t which);
  84   reg_t get_csr(int which);
  85   mmu_t* get_mmu() { return mmu; }
  86   state_t* get_state() { return &state; }
  87   extension_t* get_extension() { return ext; }
  88   void push_privilege_stack();
  89   void pop_privilege_stack();
  90   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
  91   void update_histogram(size_t pc);
  92
  93   void register_insn(insn_desc_t);
  94   void register_extension(extension_t*);
  95
  96 private:
  97   sim_t* sim;
  98   mmu_t* mmu; // main memory is always accessed via the mmu
  99   extension_t* ext;
 100   disassembler_t* disassembler;
 101   state_t state;
 102   uint32_t id;
 103   int xlen;
 104   bool run; // !reset
 105   bool debug;
 106   bool histogram_enabled;
 107   bool serialized;
 108
 109   std::vector<insn_desc_t> instructions;
 110   std::vector<insn_desc_t*> opcode_map;
 111   std::vector<insn_desc_t> opcode_store;
 112   std::map<size_t,size_t> pc_histogram;
 113
 114   void take_interrupt(); // take a trap if any interrupts are pending
 115   void serialize(); // collapse into defined architectural state
 116   reg_t take_trap(trap_t& t, reg_t epc); // take an exception
 117   void disasm(insn_t insn); // disassemble and print an instruction
 118
 119   friend class sim_t;
 120   friend class mmu_t;
 121   friend class extension_t;
 122
 123   void build_opcode_map();
 124   insn_func_t decode_insn(insn_t insn);
 125 };
 126
 127 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 128
 129 #define REGISTER_INSN(proc, name, match, mask) \
 130   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 131   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 132   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 133
 134 #endif