riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 typedef struct
  35 {
  36   uint8_t prv;
  37   bool step;
  38   bool ebreakm;
  39   bool ebreakh;
  40   bool ebreaks;
  41   bool ebreaku;
  42   bool halt;
  43   uint8_t cause;
  44 } dcsr_t;
  45
  46 // architectural state of a RISC-V hart
  47 struct state_t
  48 {
  49   void reset();
  50
  51   reg_t pc;
  52   regfile_t<reg_t, NXPR, true> XPR;
  53   regfile_t<freg_t, NFPR, false> FPR;
  54
  55   // control and status registers
  56   reg_t prv;
  57   reg_t mstatus;
  58   reg_t mepc;
  59   reg_t mbadaddr;
  60   reg_t mscratch;
  61   reg_t mtvec;
  62   reg_t mcause;
  63   reg_t minstret;
  64   reg_t mie;
  65   reg_t mip;
  66   reg_t medeleg;
  67   reg_t mideleg;
  68   reg_t mucounteren;
  69   reg_t mscounteren;
  70   reg_t sepc;
  71   reg_t sbadaddr;
  72   reg_t sscratch;
  73   reg_t stvec;
  74   reg_t sptbr;
  75   reg_t scause;
  76   reg_t dpc;
  77   reg_t dscratch;
  78   dcsr_t dcsr;
  79
  80   uint32_t fflags;
  81   uint32_t frm;
  82   bool serialized; // whether timer CSRs are in a well-defined state
  83
  84   reg_t load_reservation;
  85
  86 #ifdef RISCV_ENABLE_COMMITLOG
  87   commit_log_reg_t log_reg_write;
  88   reg_t last_inst_priv;
  89 #endif
  90 };
  91
  92 // this class represents one processor in a RISC-V machine.
  93 class processor_t : public abstract_device_t
  94 {
  95 public:
  96   processor_t(const char* isa, sim_t* sim, uint32_t id);
  97   ~processor_t();
  98
  99   void set_debug(bool value);
 100   void set_histogram(bool value);
 101   void reset(bool value);
 102   void step(size_t n); // run for n cycles
 103   bool running() { return run; }
 104   void set_csr(int which, reg_t val);
 105   void raise_interrupt(reg_t which);
 106   reg_t get_csr(int which);
 107   mmu_t* get_mmu() { return mmu; }
 108   state_t* get_state() { return &state; }
 109   extension_t* get_extension() { return ext; }
 110   bool supports_extension(unsigned char ext) {
 111     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 112     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 113   }
 114   void set_privilege(reg_t);
 115   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 116   void update_histogram(reg_t pc);
 117
 118   void register_insn(insn_desc_t);
 119   void register_extension(extension_t*);
 120
 121   // MMIO slave interface
 122   bool load(reg_t addr, size_t len, uint8_t* bytes);
 123   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 124
 125   // When true, display disassembly of each instruction that's executed.
 126   bool debug;
 127
 128 private:
 129   sim_t* sim;
 130   mmu_t* mmu; // main memory is always accessed via the mmu
 131   extension_t* ext;
 132   disassembler_t* disassembler;
 133   state_t state;
 134   uint32_t id;
 135   unsigned max_xlen;
 136   unsigned xlen;
 137   reg_t isa;
 138   std::string isa_string;
 139   bool run; // !reset
 140   bool histogram_enabled;
 141
 142   std::vector<insn_desc_t> instructions;
 143   std::map<reg_t,uint64_t> pc_histogram;
 144
 145   static const size_t OPCODE_CACHE_SIZE = 8191;
 146   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 147
 148   void check_timer();
 149   void take_interrupt(); // take a trap if any interrupts are pending
 150   void take_trap(trap_t& t, reg_t epc); // take an exception
 151   void disasm(insn_t insn); // disassemble and print an instruction
 152
 153   void enter_debug_mode(uint8_t cause);
 154
 155   friend class sim_t;
 156   friend class mmu_t;
 157   friend class rtc_t;
 158   friend class extension_t;
 159
 160   void parse_isa_string(const char* isa);
 161   void build_opcode_map();
 162   void register_base_instructions();
 163   insn_func_t decode_insn(insn_t insn);
 164 };
 165
 166 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 167
 168 #define REGISTER_INSN(proc, name, match, mask) \
 169   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 170   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 171   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 172
 173 #endif