riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 riscv_hdrs = \
   6         htif.h \
   7         common.h \
   8         decode.h \
   9         mmu.h \
  10         processor.h \
  11         sim.h \
  12         trap.h \
  13         opcodes.h \
  14         insn_header.h \
  15         dispatch.h \
  16
  17 NDISPATCH := 10
  18 DISPATCH_SRCS := \
  19         dispatch0.cc \
  20         dispatch1.cc \
  21         dispatch2.cc \
  22         dispatch3.cc \
  23         dispatch4.cc \
  24         dispatch5.cc \
  25         dispatch6.cc \
  26         dispatch7.cc \
  27         dispatch8.cc \
  28         dispatch9.cc \
  29         dispatch10.cc \
  30
  31 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
  32         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  33
  34 $(src_dir)/riscv/dispatch.h: %.h: dispatch
  35         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  36
  37 riscv_srcs = \
  38         htif.cc \
  39         processor.cc \
  40         sim.cc \
  41         interactive.cc \
  42         trap.cc \
  43         icsim.cc \
  44         mmu.cc \
  45         $(DISPATCH_SRCS) \
  46
  47 riscv_test_srcs =
  48
  49 riscv_install_prog_srcs = \
  50         riscv-isa-run.cc \