Put simif_t declaration in its own file. (#209)
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat \
6
7 riscv_install_prog_srcs = \
8
9 riscv_hdrs = \
10 common.h \
11 decode.h \
12 devices.h \
13 disasm.h \
14 dts.h \
15 mmu.h \
16 processor.h \
17 sim.h \
18 simif.h \
19 trap.h \
20 encoding.h \
21 cachesim.h \
22 memtracer.h \
23 tracer.h \
24 extension.h \
25 rocc.h \
26 insn_template.h \
27 mulhi.h \
28 debug_module.h \
29 debug_rom_defines.h \
30 remote_bitbang.h \
31 jtag_dtm.h \
32
33 riscv_precompiled_hdrs = \
34 insn_template.h \
35
36 riscv_srcs = \
37 processor.cc \
38 execute.cc \
39 dts.cc \
40 sim.cc \
41 interactive.cc \
42 trap.cc \
43 cachesim.cc \
44 mmu.cc \
45 disasm.cc \
46 extension.cc \
47 extensions.cc \
48 rocc.cc \
49 regnames.cc \
50 devices.cc \
51 rom.cc \
52 clint.cc \
53 debug_module.cc \
54 remote_bitbang.cc \
55 jtag_dtm.cc \
56 $(riscv_gen_srcs) \
57
58 riscv_test_srcs =
59
60 riscv_gen_hdrs = \
61 icache.h \
62 insn_list.h \
63
64 riscv_insn_list = \
65 add \
66 addi \
67 addiw \
68 addw \
69 amoadd_d \
70 amoadd_w \
71 amoand_d \
72 amoand_w \
73 amomax_d \
74 amomaxu_d \
75 amomaxu_w \
76 amomax_w \
77 amomin_d \
78 amominu_d \
79 amominu_w \
80 amomin_w \
81 amoor_d \
82 amoor_w \
83 amoswap_d \
84 amoswap_w \
85 amoxor_d \
86 amoxor_w \
87 and \
88 andi \
89 auipc \
90 beq \
91 bge \
92 bgeu \
93 blt \
94 bltu \
95 bne \
96 c_add \
97 c_addi4spn \
98 c_addi \
99 c_addw \
100 c_and \
101 c_andi \
102 c_beqz \
103 c_bnez \
104 c_ebreak \
105 c_fld \
106 c_fldsp \
107 c_flw \
108 c_flwsp \
109 c_fsd \
110 c_fsdsp \
111 c_fsw \
112 c_fswsp \
113 c_jal \
114 c_jalr \
115 c_j \
116 c_jr \
117 c_li \
118 c_lui \
119 c_lw \
120 c_lwsp \
121 c_mv \
122 c_or \
123 c_slli \
124 c_srai \
125 c_srli \
126 c_sub \
127 c_subw \
128 c_xor \
129 csrrc \
130 csrrci \
131 csrrs \
132 csrrsi \
133 csrrw \
134 csrrwi \
135 c_sw \
136 c_swsp \
137 div \
138 divu \
139 divuw \
140 divw \
141 dret \
142 ebreak \
143 ecall \
144 fadd_d \
145 fadd_q \
146 fadd_s \
147 fclass_d \
148 fclass_q \
149 fclass_s \
150 fcvt_d_l \
151 fcvt_d_lu \
152 fcvt_d_q \
153 fcvt_d_s \
154 fcvt_d_w \
155 fcvt_d_wu \
156 fcvt_l_d \
157 fcvt_l_q \
158 fcvt_l_s \
159 fcvt_lu_d \
160 fcvt_lu_q \
161 fcvt_lu_s \
162 fcvt_q_d \
163 fcvt_q_l \
164 fcvt_q_lu \
165 fcvt_q_s \
166 fcvt_q_w \
167 fcvt_q_wu \
168 fcvt_s_d \
169 fcvt_s_l \
170 fcvt_s_lu \
171 fcvt_s_q \
172 fcvt_s_w \
173 fcvt_s_wu \
174 fcvt_w_d \
175 fcvt_w_q \
176 fcvt_w_s \
177 fcvt_wu_d \
178 fcvt_wu_q \
179 fcvt_wu_s \
180 fdiv_d \
181 fdiv_q \
182 fdiv_s \
183 fence \
184 fence_i \
185 feq_d \
186 feq_q \
187 feq_s \
188 fld \
189 fle_d \
190 fle_q \
191 fle_s \
192 flq \
193 flt_d \
194 flt_q \
195 flt_s \
196 flw \
197 fmadd_d \
198 fmadd_q \
199 fmadd_s \
200 fmax_d \
201 fmax_q \
202 fmax_s \
203 fmin_d \
204 fmin_q \
205 fmin_s \
206 fmsub_d \
207 fmsub_q \
208 fmsub_s \
209 fmul_d \
210 fmul_q \
211 fmul_s \
212 fmv_d_x \
213 fmv_w_x \
214 fmv_x_d \
215 fmv_x_w \
216 fnmadd_d \
217 fnmadd_q \
218 fnmadd_s \
219 fnmsub_d \
220 fnmsub_q \
221 fnmsub_s \
222 fsd \
223 fsgnj_d \
224 fsgnj_q \
225 fsgnjn_d \
226 fsgnjn_q \
227 fsgnjn_s \
228 fsgnj_s \
229 fsgnjx_d \
230 fsgnjx_q \
231 fsgnjx_s \
232 fsq \
233 fsqrt_d \
234 fsqrt_q \
235 fsqrt_s \
236 fsub_d \
237 fsub_q \
238 fsub_s \
239 fsw \
240 jal \
241 jalr \
242 lb \
243 lbu \
244 ld \
245 lh \
246 lhu \
247 lr_d \
248 lr_w \
249 lui \
250 lw \
251 lwu \
252 mret \
253 mul \
254 mulh \
255 mulhsu \
256 mulhu \
257 mulw \
258 or \
259 ori \
260 rem \
261 remu \
262 remuw \
263 remw \
264 sb \
265 sc_d \
266 sc_w \
267 sd \
268 sfence_vma \
269 sh \
270 sll \
271 slli \
272 slliw \
273 sllw \
274 slt \
275 slti \
276 sltiu \
277 sltu \
278 sra \
279 srai \
280 sraiw \
281 sraw \
282 sret \
283 srl \
284 srli \
285 srliw \
286 srlw \
287 sub \
288 subw \
289 sw \
290 wfi \
291 xor \
292 xori \
293
294 riscv_gen_srcs = \
295 $(addsuffix .cc,$(riscv_insn_list))
296
297 icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
298
299 icache.h: mmu.h
300 $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
301 mv $@.tmp $@
302
303 insn_list.h: $(src_dir)/riscv/riscv.mk.in
304 for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
305 printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
306 done > $@.tmp
307 mv $@.tmp $@
308
309 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
310 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
311
312 riscv_junk = \
313 $(riscv_gen_srcs) \