Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat \
6
7 riscv_install_prog_srcs = \
8
9 riscv_hdrs = \
10 common.h \
11 decode.h \
12 devices.h \
13 disasm.h \
14 mmu.h \
15 processor.h \
16 sim.h \
17 trap.h \
18 encoding.h \
19 cachesim.h \
20 memtracer.h \
21 tracer.h \
22 extension.h \
23 rocc.h \
24 insn_template.h \
25 mulhi.h \
26 debug_module.h \
27 remote_bitbang.h \
28 jtag_dtm.h \
29
30 riscv_precompiled_hdrs = \
31 insn_template.h \
32
33 riscv_srcs = \
34 processor.cc \
35 execute.cc \
36 sim.cc \
37 interactive.cc \
38 trap.cc \
39 cachesim.cc \
40 mmu.cc \
41 disasm.cc \
42 extension.cc \
43 extensions.cc \
44 rocc.cc \
45 regnames.cc \
46 devices.cc \
47 rom.cc \
48 clint.cc \
49 debug_module.cc \
50 remote_bitbang.cc \
51 jtag_dtm.cc \
52 $(riscv_gen_srcs) \
53
54 riscv_test_srcs =
55
56 riscv_gen_hdrs = \
57 icache.h \
58 insn_list.h \
59
60 riscv_insn_list = \
61 add \
62 addi \
63 addiw \
64 addw \
65 amoadd_d \
66 amoadd_w \
67 amoand_d \
68 amoand_w \
69 amomax_d \
70 amomaxu_d \
71 amomaxu_w \
72 amomax_w \
73 amomin_d \
74 amominu_d \
75 amominu_w \
76 amomin_w \
77 amoor_d \
78 amoor_w \
79 amoswap_d \
80 amoswap_w \
81 amoxor_d \
82 amoxor_w \
83 and \
84 andi \
85 auipc \
86 beq \
87 bge \
88 bgeu \
89 blt \
90 bltu \
91 bne \
92 c_add \
93 c_addi4spn \
94 c_addi \
95 c_addw \
96 c_and \
97 c_andi \
98 c_beqz \
99 c_bnez \
100 c_ebreak \
101 c_fld \
102 c_fldsp \
103 c_flw \
104 c_flwsp \
105 c_fsd \
106 c_fsdsp \
107 c_fsw \
108 c_fswsp \
109 c_jal \
110 c_jalr \
111 c_j \
112 c_jr \
113 c_li \
114 c_lui \
115 c_lw \
116 c_lwsp \
117 c_mv \
118 c_or \
119 c_slli \
120 c_srai \
121 c_srli \
122 c_sub \
123 c_subw \
124 c_xor \
125 csrrc \
126 csrrci \
127 csrrs \
128 csrrsi \
129 csrrw \
130 csrrwi \
131 c_sw \
132 c_swsp \
133 div \
134 divu \
135 divuw \
136 divw \
137 dret \
138 ebreak \
139 ecall \
140 fadd_d \
141 fadd_q \
142 fadd_s \
143 fclass_d \
144 fclass_q \
145 fclass_s \
146 fcvt_d_l \
147 fcvt_d_lu \
148 fcvt_d_q \
149 fcvt_d_s \
150 fcvt_d_w \
151 fcvt_d_wu \
152 fcvt_l_d \
153 fcvt_l_q \
154 fcvt_l_s \
155 fcvt_lu_d \
156 fcvt_lu_q \
157 fcvt_lu_s \
158 fcvt_q_d \
159 fcvt_q_l \
160 fcvt_q_lu \
161 fcvt_q_s \
162 fcvt_q_w \
163 fcvt_q_wu \
164 fcvt_s_d \
165 fcvt_s_l \
166 fcvt_s_lu \
167 fcvt_s_q \
168 fcvt_s_w \
169 fcvt_s_wu \
170 fcvt_w_d \
171 fcvt_w_q \
172 fcvt_w_s \
173 fcvt_wu_d \
174 fcvt_wu_q \
175 fcvt_wu_s \
176 fdiv_d \
177 fdiv_q \
178 fdiv_s \
179 fence \
180 fence_i \
181 feq_d \
182 feq_q \
183 feq_s \
184 fld \
185 fle_d \
186 fle_q \
187 fle_s \
188 flq \
189 flt_d \
190 flt_q \
191 flt_s \
192 flw \
193 fmadd_d \
194 fmadd_q \
195 fmadd_s \
196 fmax_d \
197 fmax_q \
198 fmax_s \
199 fmin_d \
200 fmin_q \
201 fmin_s \
202 fmsub_d \
203 fmsub_q \
204 fmsub_s \
205 fmul_d \
206 fmul_q \
207 fmul_s \
208 fmv_d_x \
209 fmv_w_x \
210 fmv_x_d \
211 fmv_x_w \
212 fnmadd_d \
213 fnmadd_q \
214 fnmadd_s \
215 fnmsub_d \
216 fnmsub_q \
217 fnmsub_s \
218 fsd \
219 fsgnj_d \
220 fsgnj_q \
221 fsgnjn_d \
222 fsgnjn_q \
223 fsgnjn_s \
224 fsgnj_s \
225 fsgnjx_d \
226 fsgnjx_q \
227 fsgnjx_s \
228 fsq \
229 fsqrt_d \
230 fsqrt_q \
231 fsqrt_s \
232 fsub_d \
233 fsub_q \
234 fsub_s \
235 fsw \
236 jal \
237 jalr \
238 lb \
239 lbu \
240 ld \
241 lh \
242 lhu \
243 lr_d \
244 lr_w \
245 lui \
246 lw \
247 lwu \
248 mret \
249 mul \
250 mulh \
251 mulhsu \
252 mulhu \
253 mulw \
254 or \
255 ori \
256 rem \
257 remu \
258 remuw \
259 remw \
260 sb \
261 sc_d \
262 sc_w \
263 sd \
264 sfence_vma \
265 sh \
266 sll \
267 slli \
268 slliw \
269 sllw \
270 slt \
271 slti \
272 sltiu \
273 sltu \
274 sra \
275 srai \
276 sraiw \
277 sraw \
278 sret \
279 srl \
280 srli \
281 srliw \
282 srlw \
283 sub \
284 subw \
285 sw \
286 wfi \
287 xor \
288 xori \
289
290 riscv_gen_srcs = \
291 $(addsuffix .cc,$(riscv_insn_list))
292
293 icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
294
295 icache.h: mmu.h
296 $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
297 mv $@.tmp $@
298
299 insn_list.h: $(src_dir)/riscv/riscv.mk.in
300 for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
301 printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
302 done > $@.tmp
303 mv $@.tmp $@
304
305 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
306 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
307
308 riscv_junk = \
309 $(riscv_gen_srcs) \