Fix install of missed header. (#207)
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat \
6
7 riscv_install_prog_srcs = \
8
9 riscv_hdrs = \
10 common.h \
11 decode.h \
12 devices.h \
13 disasm.h \
14 dts.h \
15 mmu.h \
16 processor.h \
17 sim.h \
18 trap.h \
19 encoding.h \
20 cachesim.h \
21 memtracer.h \
22 tracer.h \
23 extension.h \
24 rocc.h \
25 insn_template.h \
26 mulhi.h \
27 debug_module.h \
28 debug_rom_defines.h \
29 remote_bitbang.h \
30 jtag_dtm.h \
31
32 riscv_precompiled_hdrs = \
33 insn_template.h \
34
35 riscv_srcs = \
36 processor.cc \
37 execute.cc \
38 dts.cc \
39 sim.cc \
40 interactive.cc \
41 trap.cc \
42 cachesim.cc \
43 mmu.cc \
44 disasm.cc \
45 extension.cc \
46 extensions.cc \
47 rocc.cc \
48 regnames.cc \
49 devices.cc \
50 rom.cc \
51 clint.cc \
52 debug_module.cc \
53 remote_bitbang.cc \
54 jtag_dtm.cc \
55 $(riscv_gen_srcs) \
56
57 riscv_test_srcs =
58
59 riscv_gen_hdrs = \
60 icache.h \
61 insn_list.h \
62
63 riscv_insn_list = \
64 add \
65 addi \
66 addiw \
67 addw \
68 amoadd_d \
69 amoadd_w \
70 amoand_d \
71 amoand_w \
72 amomax_d \
73 amomaxu_d \
74 amomaxu_w \
75 amomax_w \
76 amomin_d \
77 amominu_d \
78 amominu_w \
79 amomin_w \
80 amoor_d \
81 amoor_w \
82 amoswap_d \
83 amoswap_w \
84 amoxor_d \
85 amoxor_w \
86 and \
87 andi \
88 auipc \
89 beq \
90 bge \
91 bgeu \
92 blt \
93 bltu \
94 bne \
95 c_add \
96 c_addi4spn \
97 c_addi \
98 c_addw \
99 c_and \
100 c_andi \
101 c_beqz \
102 c_bnez \
103 c_ebreak \
104 c_fld \
105 c_fldsp \
106 c_flw \
107 c_flwsp \
108 c_fsd \
109 c_fsdsp \
110 c_fsw \
111 c_fswsp \
112 c_jal \
113 c_jalr \
114 c_j \
115 c_jr \
116 c_li \
117 c_lui \
118 c_lw \
119 c_lwsp \
120 c_mv \
121 c_or \
122 c_slli \
123 c_srai \
124 c_srli \
125 c_sub \
126 c_subw \
127 c_xor \
128 csrrc \
129 csrrci \
130 csrrs \
131 csrrsi \
132 csrrw \
133 csrrwi \
134 c_sw \
135 c_swsp \
136 div \
137 divu \
138 divuw \
139 divw \
140 dret \
141 ebreak \
142 ecall \
143 fadd_d \
144 fadd_q \
145 fadd_s \
146 fclass_d \
147 fclass_q \
148 fclass_s \
149 fcvt_d_l \
150 fcvt_d_lu \
151 fcvt_d_q \
152 fcvt_d_s \
153 fcvt_d_w \
154 fcvt_d_wu \
155 fcvt_l_d \
156 fcvt_l_q \
157 fcvt_l_s \
158 fcvt_lu_d \
159 fcvt_lu_q \
160 fcvt_lu_s \
161 fcvt_q_d \
162 fcvt_q_l \
163 fcvt_q_lu \
164 fcvt_q_s \
165 fcvt_q_w \
166 fcvt_q_wu \
167 fcvt_s_d \
168 fcvt_s_l \
169 fcvt_s_lu \
170 fcvt_s_q \
171 fcvt_s_w \
172 fcvt_s_wu \
173 fcvt_w_d \
174 fcvt_w_q \
175 fcvt_w_s \
176 fcvt_wu_d \
177 fcvt_wu_q \
178 fcvt_wu_s \
179 fdiv_d \
180 fdiv_q \
181 fdiv_s \
182 fence \
183 fence_i \
184 feq_d \
185 feq_q \
186 feq_s \
187 fld \
188 fle_d \
189 fle_q \
190 fle_s \
191 flq \
192 flt_d \
193 flt_q \
194 flt_s \
195 flw \
196 fmadd_d \
197 fmadd_q \
198 fmadd_s \
199 fmax_d \
200 fmax_q \
201 fmax_s \
202 fmin_d \
203 fmin_q \
204 fmin_s \
205 fmsub_d \
206 fmsub_q \
207 fmsub_s \
208 fmul_d \
209 fmul_q \
210 fmul_s \
211 fmv_d_x \
212 fmv_w_x \
213 fmv_x_d \
214 fmv_x_w \
215 fnmadd_d \
216 fnmadd_q \
217 fnmadd_s \
218 fnmsub_d \
219 fnmsub_q \
220 fnmsub_s \
221 fsd \
222 fsgnj_d \
223 fsgnj_q \
224 fsgnjn_d \
225 fsgnjn_q \
226 fsgnjn_s \
227 fsgnj_s \
228 fsgnjx_d \
229 fsgnjx_q \
230 fsgnjx_s \
231 fsq \
232 fsqrt_d \
233 fsqrt_q \
234 fsqrt_s \
235 fsub_d \
236 fsub_q \
237 fsub_s \
238 fsw \
239 jal \
240 jalr \
241 lb \
242 lbu \
243 ld \
244 lh \
245 lhu \
246 lr_d \
247 lr_w \
248 lui \
249 lw \
250 lwu \
251 mret \
252 mul \
253 mulh \
254 mulhsu \
255 mulhu \
256 mulw \
257 or \
258 ori \
259 rem \
260 remu \
261 remuw \
262 remw \
263 sb \
264 sc_d \
265 sc_w \
266 sd \
267 sfence_vma \
268 sh \
269 sll \
270 slli \
271 slliw \
272 sllw \
273 slt \
274 slti \
275 sltiu \
276 sltu \
277 sra \
278 srai \
279 sraiw \
280 sraw \
281 sret \
282 srl \
283 srli \
284 srliw \
285 srlw \
286 sub \
287 subw \
288 sw \
289 wfi \
290 xor \
291 xori \
292
293 riscv_gen_srcs = \
294 $(addsuffix .cc,$(riscv_insn_list))
295
296 icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
297
298 icache.h: mmu.h
299 $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
300 mv $@.tmp $@
301
302 insn_list.h: $(src_dir)/riscv/riscv.mk.in
303 for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
304 printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
305 done > $@.tmp
306 mv $@.tmp $@
307
308 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
309 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
310
311 riscv_junk = \
312 $(riscv_gen_srcs) \