riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 riscv_install_prog_srcs = \
   6         spike.cc \
   7
   8 riscv_hdrs = \
   9         htif.h \
  10         common.h \
  11         decode.h \
  12         mmu.h \
  13         processor.h \
  14         sim.h \
  15         trap.h \
  16         opcodes.h \
  17         insn_header.h \
  18         cachesim.h \
  19         memtracer.h \
  20
  21 riscv_srcs = \
  22         htif.cc \
  23         processor.cc \
  24         sim.cc \
  25         interactive.cc \
  26         trap.cc \
  27         cachesim.cc \
  28         mmu.cc \
  29         disasm.cc \
  30         $(DISPATCH_SRCS) \
  31
  32 riscv_test_srcs =
  33
  34 riscv_gen_hdrs = \
  35         dispatch.h \
  36
  37 NDISPATCH = 9
  38 DISPATCH_SRCS = $(addsuffix .cc,$(addprefix dispatch,$(shell seq 0 $(NDISPATCH))))
  39
  40 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) opcodes.h
  41         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  42
  43 dispatch.h: %.h: dispatch opcodes.h
  44         echo $(riscv_srcs)
  45         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  46
  47 riscv_junk = \
  48   dispatch.h \
  49   $(DISPATCH_SRCS) \