Extract out device-tree generation and compilation into an exported api. (#197)
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat \
6
7 riscv_install_prog_srcs = \
8
9 riscv_hdrs = \
10 common.h \
11 decode.h \
12 devices.h \
13 disasm.h \
14 dts.h \
15 mmu.h \
16 processor.h \
17 sim.h \
18 trap.h \
19 encoding.h \
20 cachesim.h \
21 memtracer.h \
22 tracer.h \
23 extension.h \
24 rocc.h \
25 insn_template.h \
26 mulhi.h \
27 debug_module.h \
28 remote_bitbang.h \
29 jtag_dtm.h \
30
31 riscv_precompiled_hdrs = \
32 insn_template.h \
33
34 riscv_srcs = \
35 processor.cc \
36 execute.cc \
37 dts.cc \
38 sim.cc \
39 interactive.cc \
40 trap.cc \
41 cachesim.cc \
42 mmu.cc \
43 disasm.cc \
44 extension.cc \
45 extensions.cc \
46 rocc.cc \
47 regnames.cc \
48 devices.cc \
49 rom.cc \
50 clint.cc \
51 debug_module.cc \
52 remote_bitbang.cc \
53 jtag_dtm.cc \
54 $(riscv_gen_srcs) \
55
56 riscv_test_srcs =
57
58 riscv_gen_hdrs = \
59 icache.h \
60 insn_list.h \
61
62 riscv_insn_list = \
63 add \
64 addi \
65 addiw \
66 addw \
67 amoadd_d \
68 amoadd_w \
69 amoand_d \
70 amoand_w \
71 amomax_d \
72 amomaxu_d \
73 amomaxu_w \
74 amomax_w \
75 amomin_d \
76 amominu_d \
77 amominu_w \
78 amomin_w \
79 amoor_d \
80 amoor_w \
81 amoswap_d \
82 amoswap_w \
83 amoxor_d \
84 amoxor_w \
85 and \
86 andi \
87 auipc \
88 beq \
89 bge \
90 bgeu \
91 blt \
92 bltu \
93 bne \
94 c_add \
95 c_addi4spn \
96 c_addi \
97 c_addw \
98 c_and \
99 c_andi \
100 c_beqz \
101 c_bnez \
102 c_ebreak \
103 c_fld \
104 c_fldsp \
105 c_flw \
106 c_flwsp \
107 c_fsd \
108 c_fsdsp \
109 c_fsw \
110 c_fswsp \
111 c_jal \
112 c_jalr \
113 c_j \
114 c_jr \
115 c_li \
116 c_lui \
117 c_lw \
118 c_lwsp \
119 c_mv \
120 c_or \
121 c_slli \
122 c_srai \
123 c_srli \
124 c_sub \
125 c_subw \
126 c_xor \
127 csrrc \
128 csrrci \
129 csrrs \
130 csrrsi \
131 csrrw \
132 csrrwi \
133 c_sw \
134 c_swsp \
135 div \
136 divu \
137 divuw \
138 divw \
139 dret \
140 ebreak \
141 ecall \
142 fadd_d \
143 fadd_q \
144 fadd_s \
145 fclass_d \
146 fclass_q \
147 fclass_s \
148 fcvt_d_l \
149 fcvt_d_lu \
150 fcvt_d_q \
151 fcvt_d_s \
152 fcvt_d_w \
153 fcvt_d_wu \
154 fcvt_l_d \
155 fcvt_l_q \
156 fcvt_l_s \
157 fcvt_lu_d \
158 fcvt_lu_q \
159 fcvt_lu_s \
160 fcvt_q_d \
161 fcvt_q_l \
162 fcvt_q_lu \
163 fcvt_q_s \
164 fcvt_q_w \
165 fcvt_q_wu \
166 fcvt_s_d \
167 fcvt_s_l \
168 fcvt_s_lu \
169 fcvt_s_q \
170 fcvt_s_w \
171 fcvt_s_wu \
172 fcvt_w_d \
173 fcvt_w_q \
174 fcvt_w_s \
175 fcvt_wu_d \
176 fcvt_wu_q \
177 fcvt_wu_s \
178 fdiv_d \
179 fdiv_q \
180 fdiv_s \
181 fence \
182 fence_i \
183 feq_d \
184 feq_q \
185 feq_s \
186 fld \
187 fle_d \
188 fle_q \
189 fle_s \
190 flq \
191 flt_d \
192 flt_q \
193 flt_s \
194 flw \
195 fmadd_d \
196 fmadd_q \
197 fmadd_s \
198 fmax_d \
199 fmax_q \
200 fmax_s \
201 fmin_d \
202 fmin_q \
203 fmin_s \
204 fmsub_d \
205 fmsub_q \
206 fmsub_s \
207 fmul_d \
208 fmul_q \
209 fmul_s \
210 fmv_d_x \
211 fmv_w_x \
212 fmv_x_d \
213 fmv_x_w \
214 fnmadd_d \
215 fnmadd_q \
216 fnmadd_s \
217 fnmsub_d \
218 fnmsub_q \
219 fnmsub_s \
220 fsd \
221 fsgnj_d \
222 fsgnj_q \
223 fsgnjn_d \
224 fsgnjn_q \
225 fsgnjn_s \
226 fsgnj_s \
227 fsgnjx_d \
228 fsgnjx_q \
229 fsgnjx_s \
230 fsq \
231 fsqrt_d \
232 fsqrt_q \
233 fsqrt_s \
234 fsub_d \
235 fsub_q \
236 fsub_s \
237 fsw \
238 jal \
239 jalr \
240 lb \
241 lbu \
242 ld \
243 lh \
244 lhu \
245 lr_d \
246 lr_w \
247 lui \
248 lw \
249 lwu \
250 mret \
251 mul \
252 mulh \
253 mulhsu \
254 mulhu \
255 mulw \
256 or \
257 ori \
258 rem \
259 remu \
260 remuw \
261 remw \
262 sb \
263 sc_d \
264 sc_w \
265 sd \
266 sfence_vma \
267 sh \
268 sll \
269 slli \
270 slliw \
271 sllw \
272 slt \
273 slti \
274 sltiu \
275 sltu \
276 sra \
277 srai \
278 sraiw \
279 sraw \
280 sret \
281 srl \
282 srli \
283 srliw \
284 srlw \
285 sub \
286 subw \
287 sw \
288 wfi \
289 xor \
290 xori \
291
292 riscv_gen_srcs = \
293 $(addsuffix .cc,$(riscv_insn_list))
294
295 icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
296
297 icache.h: mmu.h
298 $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
299 mv $@.tmp $@
300
301 insn_list.h: $(src_dir)/riscv/riscv.mk.in
302 for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
303 printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
304 done > $@.tmp
305 mv $@.tmp $@
306
307 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
308 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
309
310 riscv_junk = \
311 $(riscv_gen_srcs) \