riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 repo_hdrs := \
   6         htif.h \
   7         common.h \
   8         decode.h \
   9         mmu.h \
  10         processor.h \
  11         sim.h \
  12         trap.h \
  13         opcodes.h \
  14         insn_header.h \
  15         cachesim.h \
  16         memtracer.h \
  17
  18 riscv_hdrs := \
  19         $(repo_hdrs) \
  20         dispatch.h
  21
  22
  23 NDISPATCH := 10
  24 DISPATCH_SRCS := \
  25         dispatch0.cc \
  26         dispatch1.cc \
  27         dispatch2.cc \
  28         dispatch3.cc \
  29         dispatch4.cc \
  30         dispatch5.cc \
  31         dispatch6.cc \
  32         dispatch7.cc \
  33         dispatch8.cc \
  34         dispatch9.cc \
  35         dispatch10.cc \
  36
  37 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
  38         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  39
  40 dispatch.h: %.h: dispatch $(repo_hdrs)
  41         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  42
  43 riscv_srcs = \
  44         htif.cc \
  45         processor.cc \
  46         sim.cc \
  47         interactive.cc \
  48         trap.cc \
  49         cachesim.cc \
  50         mmu.cc \
  51         disasm.cc \
  52         $(DISPATCH_SRCS) \
  53
  54 riscv_test_srcs =
  55
  56 riscv_install_prog_srcs = \
  57         riscv-isa-run.cc \