riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 riscv_hdrs = \
   6         htif.h \
   7         common.h \
   8         decode.h \
   9         mmu.h \
  10         processor.h \
  11         sim.h \
  12         trap.h \
  13         opcodes.h \
  14         insn_header.h \
  15         dispatch.h \
  16         cachesim.h \
  17         memtracer.h \
  18
  19 NDISPATCH := 10
  20 DISPATCH_SRCS := \
  21         dispatch0.cc \
  22         dispatch1.cc \
  23         dispatch2.cc \
  24         dispatch3.cc \
  25         dispatch4.cc \
  26         dispatch5.cc \
  27         dispatch6.cc \
  28         dispatch7.cc \
  29         dispatch8.cc \
  30         dispatch9.cc \
  31         dispatch10.cc \
  32
  33 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
  34         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  35
  36 dispatch.h: %.h: dispatch $(riscv_hdrs)
  37         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  38
  39 riscv_srcs = \
  40         htif.cc \
  41         processor.cc \
  42         sim.cc \
  43         interactive.cc \
  44         trap.cc \
  45         cachesim.cc \
  46         mmu.cc \
  47         disasm.cc \
  48         $(DISPATCH_SRCS) \
  49
  50 riscv_test_srcs =
  51
  52 riscv_install_prog_srcs = \
  53         riscv-isa-run.cc \