riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 riscv_install_prog_srcs = \
   6         spike.cc \
   7         xspike.cc \
   8         termios-xspike.cc \
   9
  10 riscv_hdrs = \
  11         htif.h \
  12         common.h \
  13         decode.h \
  14         mmu.h \
  15         processor.h \
  16         sim.h \
  17         trap.h \
  18         opcodes.h \
  19         insn_header.h \
  20         cachesim.h \
  21         memtracer.h \
  22
  23 riscv_srcs = \
  24         htif.cc \
  25         processor.cc \
  26         sim.cc \
  27         interactive.cc \
  28         trap.cc \
  29         cachesim.cc \
  30         mmu.cc \
  31         disasm.cc \
  32         $(DISPATCH_SRCS) \
  33
  34 riscv_test_srcs =
  35
  36 riscv_gen_hdrs = \
  37         dispatch.h \
  38
  39 NDISPATCH = 9
  40 DISPATCH_SRCS = $(addsuffix .cc,$(addprefix dispatch,$(shell seq 0 $(NDISPATCH))))
  41
  42 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) opcodes.h
  43         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  44
  45 dispatch.h: %.h: dispatch opcodes.h
  46         echo $(riscv_srcs)
  47         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  48
  49 riscv_junk = \
  50   dispatch.h \
  51   $(DISPATCH_SRCS) \