Merge branch 'confprec'
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
2 get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
3
4 riscv_subproject_deps = \
5 softfloat_riscv \
6 softfloat \
7 hwacha \
8
9 riscv_install_prog_srcs = \
10 spike.cc \
11 riscv-dis.cc \
12 xspike.cc \
13 termios-xspike.cc \
14
15 riscv_hdrs = \
16 htif.h \
17 common.h \
18 decode.h \
19 mmu.h \
20 processor.h \
21 sim.h \
22 trap.h \
23 encoding.h \
24 cachesim.h \
25 memtracer.h \
26 extension.h \
27 rocc.h \
28 dummy-rocc.h \
29
30 riscv_srcs = \
31 htif.cc \
32 processor.cc \
33 sim.cc \
34 interactive.cc \
35 trap.cc \
36 cachesim.cc \
37 mmu.cc \
38 disasm.cc \
39 extension.cc \
40 rocc.cc \
41 $(riscv_gen_srcs) \
42
43 riscv_test_srcs =
44
45 riscv_gen_hdrs = \
46 icache.h \
47
48 riscv_gen_srcs = \
49 $(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/encoding.h))
50
51 icache.h:
52 $(src_dir)/riscv/gen_icache 1024 > $@
53
54 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
55 sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
56
57 riscv_junk = \
58 $(riscv_gen_srcs) \