riscv/riscv.mk.in

   1 riscv_subproject_deps = \
   2         softfloat_riscv \
   3         softfloat \
   4
   5 riscv_hdrs := \
   6         htif.h \
   7         common.h \
   8         decode.h \
   9         mmu.h \
  10         processor.h \
  11         sim.h \
  12         trap.h \
  13         opcodes.h \
  14         insn_header.h \
  15         cachesim.h \
  16         memtracer.h \
  17         dispatch.h \
  18
  19 NDISPATCH := 9
  20 DISPATCH_SRCS := \
  21         dispatch0.cc \
  22         dispatch1.cc \
  23         dispatch2.cc \
  24         dispatch3.cc \
  25         dispatch4.cc \
  26         dispatch5.cc \
  27         dispatch6.cc \
  28         dispatch7.cc \
  29         dispatch8.cc \
  30         dispatch9.cc \
  31
  32 $(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) opcodes.h
  33         $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  34
  35 $(src_dir)/riscv/dispatch.h: %.h: dispatch opcodes.h
  36         $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
  37
  38 riscv_srcs = \
  39         htif.cc \
  40         processor.cc \
  41         sim.cc \
  42         interactive.cc \
  43         trap.cc \
  44         cachesim.cc \
  45         mmu.cc \
  46         disasm.cc \
  47         $(DISPATCH_SRCS) \
  48
  49 riscv_test_srcs =
  50
  51 riscv_install_prog_srcs = \
  52         riscv-isa-run.cc \