[sim,opcodes] improved sim build and run performance
[riscv-isa-sim.git] / riscv / riscv.mk.in
1 riscv_subproject_deps = \
2 softfloat_riscv \
3 softfloat \
4
5 riscv_hdrs = \
6 applink.h \
7 common.h \
8 decode.h \
9 dispatch.h \
10 mmu.h \
11 processor.h \
12 sim.h \
13 trap.h \
14 insns/*.h \
15
16 riscv_srcs = \
17 applink.cc \
18 processor.cc \
19 sim.cc \
20 trap.cc \
21 icsim.cc \
22 mmu.cc \
23 dispatch_0.cc \
24 dispatch_1.cc \
25 dispatch_2.cc \
26 dispatch_3.cc \
27 dispatch_4.cc \
28 dispatch_5.cc \
29 dispatch_6.cc \
30 dispatch_7.cc \
31 dispatch_8.cc \
32 dispatch_9.cc \
33
34 riscv_test_srcs =
35
36 riscv_install_prog_srcs = \
37 riscv-isa-run.cc \