Merge pull request #117 from riscv/multicore_debug
[riscv-isa-sim.git] / riscv / rocc.h
1 #ifndef _RISCV_ROCC_H
2 #define _RISCV_ROCC_H
3
4 #include "extension.h"
5
6 struct rocc_insn_t
7 {
8 unsigned opcode : 7;
9 unsigned rd : 5;
10 unsigned xs2 : 1;
11 unsigned xs1 : 1;
12 unsigned xd : 1;
13 unsigned rs1 : 5;
14 unsigned rs2 : 5;
15 unsigned funct : 7;
16 };
17
18 union rocc_insn_union_t
19 {
20 rocc_insn_t r;
21 insn_t i;
22 };
23
24 class rocc_t : public extension_t
25 {
26 public:
27 virtual reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2);
28 virtual reg_t custom1(rocc_insn_t insn, reg_t xs1, reg_t xs2);
29 virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2);
30 virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2);
31 std::vector<insn_desc_t> get_instructions();
32 std::vector<disasm_insn_t*> get_disasms();
33 };
34
35 #endif