riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "remote_bitbang.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args,
  29              std::vector<int> const hartids, unsigned progsize,
  30              unsigned max_bus_master_bits)
  31   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
  32     start_pc(start_pc), current_step(0), current_proc(0), debug(false),
  33     remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits)
  34 {
  35   signal(SIGINT, &handle_signal);
  36
  37   for (auto& x : mems)
  38     bus.add_device(x.first, x.second);
  39
  40   debug_module.add_device(&bus);
  41
  42   debug_mmu = new mmu_t(this, NULL);
  43
  44   if (hartids.size() == 0) {
  45     for (size_t i = 0; i < procs.size(); i++) {
  46       procs[i] = new processor_t(isa, this, i, halted);
  47     }
  48   }
  49   else {
  50     if (hartids.size() != procs.size()) {
  51       std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
  52       exit(1);
  53     }
  54     for (size_t i = 0; i < procs.size(); i++) {
  55       procs[i] = new processor_t(isa, this, hartids[i], halted);
  56     }
  57   }
  58
  59   clint.reset(new clint_t(procs));
  60   bus.add_device(CLINT_BASE, clint.get());
  61 }
  62
  63 sim_t::~sim_t()
  64 {
  65   for (size_t i = 0; i < procs.size(); i++)
  66     delete procs[i];
  67   delete debug_mmu;
  68 }
  69
  70 void sim_thread_main(void* arg)
  71 {
  72   ((sim_t*)arg)->main();
  73 }
  74
  75 void sim_t::main()
  76 {
  77   if (!debug && log)
  78     set_procs_debug(true);
  79
  80   while (!done())
  81   {
  82     if (debug || ctrlc_pressed)
  83       interactive();
  84     else
  85       step(INTERLEAVE);
  86     if (remote_bitbang) {
  87       remote_bitbang->tick();
  88     }
  89   }
  90 }
  91
  92 int sim_t::run()
  93 {
  94   host = context_t::current();
  95   target.init(sim_thread_main, this);
  96   return htif_t::run();
  97 }
  98
  99 void sim_t::step(size_t n)
 100 {
 101   for (size_t i = 0, steps = 0; i < n; i += steps)
 102   {
 103     steps = std::min(n - i, INTERLEAVE - current_step);
 104     procs[current_proc]->step(steps);
 105
 106     current_step += steps;
 107     if (current_step == INTERLEAVE)
 108     {
 109       current_step = 0;
 110       procs[current_proc]->yield_load_reservation();
 111       if (++current_proc == procs.size()) {
 112         current_proc = 0;
 113         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 114       }
 115
 116       host->switch_to();
 117     }
 118   }
 119 }
 120
 121 void sim_t::set_debug(bool value)
 122 {
 123   debug = value;
 124 }
 125
 126 void sim_t::set_log(bool value)
 127 {
 128   log = value;
 129 }
 130
 131 void sim_t::set_histogram(bool value)
 132 {
 133   histogram_enabled = value;
 134   for (size_t i = 0; i < procs.size(); i++) {
 135     procs[i]->set_histogram(histogram_enabled);
 136   }
 137 }
 138
 139 void sim_t::set_procs_debug(bool value)
 140 {
 141   for (size_t i=0; i< procs.size(); i++)
 142     procs[i]->set_debug(value);
 143 }
 144
 145 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 146 {
 147   if (addr + len < addr)
 148     return false;
 149   return bus.load(addr, len, bytes);
 150 }
 151
 152 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 153 {
 154   if (addr + len < addr)
 155     return false;
 156   return bus.store(addr, len, bytes);
 157 }
 158
 159 static std::string dts_compile(const std::string& dts)
 160 {
 161   // Convert the DTS to DTB
 162   int dts_pipe[2];
 163   pid_t dts_pid;
 164
 165   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 166     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 167     exit(1);
 168   }
 169
 170   // Child process to output dts
 171   if (dts_pid == 0) {
 172     close(dts_pipe[0]);
 173     int step, len = dts.length();
 174     const char *buf = dts.c_str();
 175     for (int done = 0; done < len; done += step) {
 176       step = write(dts_pipe[1], buf+done, len-done);
 177       if (step == -1) {
 178         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 179         exit(1);
 180       }
 181     }
 182     close(dts_pipe[1]);
 183     exit(0);
 184   }
 185
 186   pid_t dtb_pid;
 187   int dtb_pipe[2];
 188   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 189     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 190     exit(1);
 191   }
 192
 193   // Child process to output dtb
 194   if (dtb_pid == 0) {
 195     dup2(dts_pipe[0], 0);
 196     dup2(dtb_pipe[1], 1);
 197     close(dts_pipe[0]);
 198     close(dts_pipe[1]);
 199     close(dtb_pipe[0]);
 200     close(dtb_pipe[1]);
 201     execl(DTC, DTC, "-O", "dtb", 0);
 202     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 203     exit(1);
 204   }
 205
 206   close(dts_pipe[1]);
 207   close(dts_pipe[0]);
 208   close(dtb_pipe[1]);
 209
 210   // Read-out dtb
 211   std::stringstream dtb;
 212
 213   int got;
 214   char buf[4096];
 215   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 216     dtb.write(buf, got);
 217   }
 218   if (got == -1) {
 219     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 220     exit(1);
 221   }
 222   close(dtb_pipe[0]);
 223
 224   // Reap children
 225   int status;
 226   waitpid(dts_pid, &status, 0);
 227   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 228     std::cerr << "Child dts process failed" << std::endl;
 229     exit(1);
 230   }
 231   waitpid(dtb_pid, &status, 0);
 232   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 233     std::cerr << "Child dtb process failed" << std::endl;
 234     exit(1);
 235   }
 236
 237   return dtb.str();
 238 }
 239
 240 void sim_t::make_dtb()
 241 {
 242   const int reset_vec_size = 8;
 243
 244   start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
 245
 246   uint32_t reset_vec[reset_vec_size] = {
 247     0x297,                                      // auipc  t0,0x0
 248     0x28593 + (reset_vec_size * 4 << 20),       // addi   a1, t0, &dtb
 249     0xf1402573,                                 // csrr   a0, mhartid
 250     get_core(0)->xlen == 32 ?
 251       0x0182a283u :                             // lw     t0,24(t0)
 252       0x0182b283u,                              // ld     t0,24(t0)
 253     0x28067,                                    // jr     t0
 254     0,
 255     (uint32_t) (start_pc & 0xffffffff),
 256     (uint32_t) (start_pc >> 32)
 257   };
 258
 259   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 260
 261   std::stringstream s;
 262   s << std::dec <<
 263          "/dts-v1/;\n"
 264          "\n"
 265          "/ {\n"
 266          "  #address-cells = <2>;\n"
 267          "  #size-cells = <2>;\n"
 268          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 269          "  model = \"ucbbar,spike-bare\";\n"
 270          "  cpus {\n"
 271          "    #address-cells = <1>;\n"
 272          "    #size-cells = <0>;\n"
 273          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 274   for (size_t i = 0; i < procs.size(); i++) {
 275     s << "    CPU" << i << ": cpu@" << i << " {\n"
 276          "      device_type = \"cpu\";\n"
 277          "      reg = <" << i << ">;\n"
 278          "      status = \"okay\";\n"
 279          "      compatible = \"riscv\";\n"
 280          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 281          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 282          "      clock-frequency = <" << CPU_HZ << ">;\n"
 283          "      CPU" << i << "_intc: interrupt-controller {\n"
 284          "        #interrupt-cells = <1>;\n"
 285          "        interrupt-controller;\n"
 286          "        compatible = \"riscv,cpu-intc\";\n"
 287          "      };\n"
 288          "    };\n";
 289   }
 290   s <<   "  };\n";
 291   for (auto& m : mems) {
 292     s << std::hex <<
 293          "  memory@" << m.first << " {\n"
 294          "    device_type = \"memory\";\n"
 295          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 296                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 297          "  };\n";
 298   }
 299   s <<   "  soc {\n"
 300          "    #address-cells = <2>;\n"
 301          "    #size-cells = <2>;\n"
 302          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 303          "    ranges;\n"
 304          "    clint@" << CLINT_BASE << " {\n"
 305          "      compatible = \"riscv,clint0\";\n"
 306          "      interrupts-extended = <" << std::dec;
 307   for (size_t i = 0; i < procs.size(); i++)
 308     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 309   reg_t clintbs = CLINT_BASE;
 310   reg_t clintsz = CLINT_SIZE;
 311   s << std::hex << ">;\n"
 312          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 313                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 314          "    };\n"
 315          "  };\n"
 316          "  htif {\n"
 317          "    compatible = \"ucb,htif0\";\n"
 318          "  };\n"
 319          "};\n";
 320
 321   dts = s.str();
 322   std::string dtb = dts_compile(dts);
 323
 324   rom.insert(rom.end(), dtb.begin(), dtb.end());
 325   const int align = 0x1000;
 326   rom.resize((rom.size() + align - 1) / align * align);
 327
 328   boot_rom.reset(new rom_device_t(rom));
 329   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 330 }
 331
 332 char* sim_t::addr_to_mem(reg_t addr) {
 333   auto desc = bus.find_device(addr);
 334   if (auto mem = dynamic_cast<mem_t*>(desc.second))
 335     if (addr - desc.first < mem->size())
 336       return mem->contents() + (addr - desc.first);
 337   return NULL;
 338 }
 339
 340 // htif
 341
 342 void sim_t::reset()
 343 {
 344   make_dtb();
 345 }
 346
 347 void sim_t::idle()
 348 {
 349   target.switch_to();
 350 }
 351
 352 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 353 {
 354   assert(len == 8);
 355   auto data = debug_mmu->load_uint64(taddr);
 356   memcpy(dst, &data, sizeof data);
 357 }
 358
 359 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 360 {
 361   assert(len == 8);
 362   uint64_t data;
 363   memcpy(&data, src, sizeof data);
 364   debug_mmu->store_uint64(taddr, data);
 365 }