riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "remote_bitbang.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args,
  29              std::vector<int> const hartids, unsigned progsize,
  30              unsigned max_bus_master_bits, bool require_authentication)
  31   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
  32     start_pc(start_pc), current_step(0), current_proc(0), debug(false),
  33     remote_bitbang(NULL),
  34     debug_module(this, progsize, max_bus_master_bits, require_authentication)
  35 {
  36   signal(SIGINT, &handle_signal);
  37
  38   for (auto& x : mems)
  39     bus.add_device(x.first, x.second);
  40
  41   debug_module.add_device(&bus);
  42
  43   debug_mmu = new mmu_t(this, NULL);
  44
  45   if (hartids.size() == 0) {
  46     for (size_t i = 0; i < procs.size(); i++) {
  47       procs[i] = new processor_t(isa, this, i, halted);
  48     }
  49   }
  50   else {
  51     if (hartids.size() != procs.size()) {
  52       std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
  53       exit(1);
  54     }
  55     for (size_t i = 0; i < procs.size(); i++) {
  56       procs[i] = new processor_t(isa, this, hartids[i], halted);
  57     }
  58   }
  59
  60   clint.reset(new clint_t(procs));
  61   bus.add_device(CLINT_BASE, clint.get());
  62 }
  63
  64 sim_t::~sim_t()
  65 {
  66   for (size_t i = 0; i < procs.size(); i++)
  67     delete procs[i];
  68   delete debug_mmu;
  69 }
  70
  71 void sim_thread_main(void* arg)
  72 {
  73   ((sim_t*)arg)->main();
  74 }
  75
  76 void sim_t::main()
  77 {
  78   if (!debug && log)
  79     set_procs_debug(true);
  80
  81   while (!done())
  82   {
  83     if (debug || ctrlc_pressed)
  84       interactive();
  85     else
  86       step(INTERLEAVE);
  87     if (remote_bitbang) {
  88       remote_bitbang->tick();
  89     }
  90   }
  91 }
  92
  93 int sim_t::run()
  94 {
  95   host = context_t::current();
  96   target.init(sim_thread_main, this);
  97   return htif_t::run();
  98 }
  99
 100 void sim_t::step(size_t n)
 101 {
 102   for (size_t i = 0, steps = 0; i < n; i += steps)
 103   {
 104     steps = std::min(n - i, INTERLEAVE - current_step);
 105     procs[current_proc]->step(steps);
 106
 107     current_step += steps;
 108     if (current_step == INTERLEAVE)
 109     {
 110       current_step = 0;
 111       procs[current_proc]->yield_load_reservation();
 112       if (++current_proc == procs.size()) {
 113         current_proc = 0;
 114         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 115       }
 116
 117       host->switch_to();
 118     }
 119   }
 120 }
 121
 122 void sim_t::set_debug(bool value)
 123 {
 124   debug = value;
 125 }
 126
 127 void sim_t::set_log(bool value)
 128 {
 129   log = value;
 130 }
 131
 132 void sim_t::set_histogram(bool value)
 133 {
 134   histogram_enabled = value;
 135   for (size_t i = 0; i < procs.size(); i++) {
 136     procs[i]->set_histogram(histogram_enabled);
 137   }
 138 }
 139
 140 void sim_t::set_procs_debug(bool value)
 141 {
 142   for (size_t i=0; i< procs.size(); i++)
 143     procs[i]->set_debug(value);
 144 }
 145
 146 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 147 {
 148   if (addr + len < addr)
 149     return false;
 150   return bus.load(addr, len, bytes);
 151 }
 152
 153 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 154 {
 155   if (addr + len < addr)
 156     return false;
 157   return bus.store(addr, len, bytes);
 158 }
 159
 160 static std::string dts_compile(const std::string& dts)
 161 {
 162   // Convert the DTS to DTB
 163   int dts_pipe[2];
 164   pid_t dts_pid;
 165
 166   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 167     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 168     exit(1);
 169   }
 170
 171   // Child process to output dts
 172   if (dts_pid == 0) {
 173     close(dts_pipe[0]);
 174     int step, len = dts.length();
 175     const char *buf = dts.c_str();
 176     for (int done = 0; done < len; done += step) {
 177       step = write(dts_pipe[1], buf+done, len-done);
 178       if (step == -1) {
 179         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 180         exit(1);
 181       }
 182     }
 183     close(dts_pipe[1]);
 184     exit(0);
 185   }
 186
 187   pid_t dtb_pid;
 188   int dtb_pipe[2];
 189   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 190     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 191     exit(1);
 192   }
 193
 194   // Child process to output dtb
 195   if (dtb_pid == 0) {
 196     dup2(dts_pipe[0], 0);
 197     dup2(dtb_pipe[1], 1);
 198     close(dts_pipe[0]);
 199     close(dts_pipe[1]);
 200     close(dtb_pipe[0]);
 201     close(dtb_pipe[1]);
 202     execl(DTC, DTC, "-O", "dtb", 0);
 203     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 204     exit(1);
 205   }
 206
 207   close(dts_pipe[1]);
 208   close(dts_pipe[0]);
 209   close(dtb_pipe[1]);
 210
 211   // Read-out dtb
 212   std::stringstream dtb;
 213
 214   int got;
 215   char buf[4096];
 216   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 217     dtb.write(buf, got);
 218   }
 219   if (got == -1) {
 220     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 221     exit(1);
 222   }
 223   close(dtb_pipe[0]);
 224
 225   // Reap children
 226   int status;
 227   waitpid(dts_pid, &status, 0);
 228   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 229     std::cerr << "Child dts process failed" << std::endl;
 230     exit(1);
 231   }
 232   waitpid(dtb_pid, &status, 0);
 233   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 234     std::cerr << "Child dtb process failed" << std::endl;
 235     exit(1);
 236   }
 237
 238   return dtb.str();
 239 }
 240
 241 void sim_t::make_dtb()
 242 {
 243   const int reset_vec_size = 8;
 244
 245   start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
 246
 247   uint32_t reset_vec[reset_vec_size] = {
 248     0x297,                                      // auipc  t0,0x0
 249     0x28593 + (reset_vec_size * 4 << 20),       // addi   a1, t0, &dtb
 250     0xf1402573,                                 // csrr   a0, mhartid
 251     get_core(0)->xlen == 32 ?
 252       0x0182a283u :                             // lw     t0,24(t0)
 253       0x0182b283u,                              // ld     t0,24(t0)
 254     0x28067,                                    // jr     t0
 255     0,
 256     (uint32_t) (start_pc & 0xffffffff),
 257     (uint32_t) (start_pc >> 32)
 258   };
 259
 260   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 261
 262   std::stringstream s;
 263   s << std::dec <<
 264          "/dts-v1/;\n"
 265          "\n"
 266          "/ {\n"
 267          "  #address-cells = <2>;\n"
 268          "  #size-cells = <2>;\n"
 269          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 270          "  model = \"ucbbar,spike-bare\";\n"
 271          "  cpus {\n"
 272          "    #address-cells = <1>;\n"
 273          "    #size-cells = <0>;\n"
 274          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 275   for (size_t i = 0; i < procs.size(); i++) {
 276     s << "    CPU" << i << ": cpu@" << i << " {\n"
 277          "      device_type = \"cpu\";\n"
 278          "      reg = <" << i << ">;\n"
 279          "      status = \"okay\";\n"
 280          "      compatible = \"riscv\";\n"
 281          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 282          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 283          "      clock-frequency = <" << CPU_HZ << ">;\n"
 284          "      CPU" << i << "_intc: interrupt-controller {\n"
 285          "        #interrupt-cells = <1>;\n"
 286          "        interrupt-controller;\n"
 287          "        compatible = \"riscv,cpu-intc\";\n"
 288          "      };\n"
 289          "    };\n";
 290   }
 291   s <<   "  };\n";
 292   for (auto& m : mems) {
 293     s << std::hex <<
 294          "  memory@" << m.first << " {\n"
 295          "    device_type = \"memory\";\n"
 296          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 297                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 298          "  };\n";
 299   }
 300   s <<   "  soc {\n"
 301          "    #address-cells = <2>;\n"
 302          "    #size-cells = <2>;\n"
 303          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 304          "    ranges;\n"
 305          "    clint@" << CLINT_BASE << " {\n"
 306          "      compatible = \"riscv,clint0\";\n"
 307          "      interrupts-extended = <" << std::dec;
 308   for (size_t i = 0; i < procs.size(); i++)
 309     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 310   reg_t clintbs = CLINT_BASE;
 311   reg_t clintsz = CLINT_SIZE;
 312   s << std::hex << ">;\n"
 313          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 314                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 315          "    };\n"
 316          "  };\n"
 317          "  htif {\n"
 318          "    compatible = \"ucb,htif0\";\n"
 319          "  };\n"
 320          "};\n";
 321
 322   dts = s.str();
 323   std::string dtb = dts_compile(dts);
 324
 325   rom.insert(rom.end(), dtb.begin(), dtb.end());
 326   const int align = 0x1000;
 327   rom.resize((rom.size() + align - 1) / align * align);
 328
 329   boot_rom.reset(new rom_device_t(rom));
 330   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 331 }
 332
 333 char* sim_t::addr_to_mem(reg_t addr) {
 334   auto desc = bus.find_device(addr);
 335   if (auto mem = dynamic_cast<mem_t*>(desc.second))
 336     if (addr - desc.first < mem->size())
 337       return mem->contents() + (addr - desc.first);
 338   return NULL;
 339 }
 340
 341 // htif
 342
 343 void sim_t::reset()
 344 {
 345   make_dtb();
 346 }
 347
 348 void sim_t::idle()
 349 {
 350   target.switch_to();
 351 }
 352
 353 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 354 {
 355   assert(len == 8);
 356   auto data = debug_mmu->load_uint64(taddr);
 357   memcpy(dst, &data, sizeof data);
 358 }
 359
 360 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 361 {
 362   assert(len == 8);
 363   uint64_t data;
 364   memcpy(&data, src, sizeof data);
 365   debug_mmu->store_uint64(taddr, data);
 366 }