riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "remote_bitbang.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args, std::vector<int> const hartids)
  29   : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))),
  30     start_pc(start_pc),
  31     current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
  32 {
  33   signal(SIGINT, &handle_signal);
  34
  35   for (auto& x : mems)
  36     bus.add_device(x.first, x.second);
  37
  38   debug_module.add_device(&bus);
  39
  40   debug_mmu = new mmu_t(this, NULL);
  41
  42   if (hartids.size() == 0) {
  43     for (size_t i = 0; i < procs.size(); i++) {
  44       procs[i] = new processor_t(isa, this, i, halted);
  45     }
  46   }
  47   else {
  48     if (hartids.size() != procs.size()) {
  49       std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
  50       exit(1);
  51     }
  52     for (size_t i = 0; i < procs.size(); i++) {
  53       procs[i] = new processor_t(isa, this, hartids[i], halted);
  54     }
  55   }
  56
  57   clint.reset(new clint_t(procs));
  58   bus.add_device(CLINT_BASE, clint.get());
  59 }
  60
  61 sim_t::~sim_t()
  62 {
  63   for (size_t i = 0; i < procs.size(); i++)
  64     delete procs[i];
  65   delete debug_mmu;
  66 }
  67
  68 void sim_thread_main(void* arg)
  69 {
  70   ((sim_t*)arg)->main();
  71 }
  72
  73 void sim_t::main()
  74 {
  75   if (!debug && log)
  76     set_procs_debug(true);
  77
  78   while (!done())
  79   {
  80     if (debug || ctrlc_pressed)
  81       interactive();
  82     else
  83       step(INTERLEAVE);
  84     if (remote_bitbang) {
  85       remote_bitbang->tick();
  86     }
  87   }
  88 }
  89
  90 int sim_t::run()
  91 {
  92   host = context_t::current();
  93   target.init(sim_thread_main, this);
  94   return htif_t::run();
  95 }
  96
  97 void sim_t::step(size_t n)
  98 {
  99   for (size_t i = 0, steps = 0; i < n; i += steps)
 100   {
 101     steps = std::min(n - i, INTERLEAVE - current_step);
 102     procs[current_proc]->step(steps);
 103
 104     current_step += steps;
 105     if (current_step == INTERLEAVE)
 106     {
 107       current_step = 0;
 108       procs[current_proc]->yield_load_reservation();
 109       if (++current_proc == procs.size()) {
 110         current_proc = 0;
 111         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 112       }
 113
 114       host->switch_to();
 115     }
 116   }
 117 }
 118
 119 void sim_t::set_debug(bool value)
 120 {
 121   debug = value;
 122 }
 123
 124 void sim_t::set_log(bool value)
 125 {
 126   log = value;
 127 }
 128
 129 void sim_t::set_histogram(bool value)
 130 {
 131   histogram_enabled = value;
 132   for (size_t i = 0; i < procs.size(); i++) {
 133     procs[i]->set_histogram(histogram_enabled);
 134   }
 135 }
 136
 137 void sim_t::set_procs_debug(bool value)
 138 {
 139   for (size_t i=0; i< procs.size(); i++)
 140     procs[i]->set_debug(value);
 141 }
 142
 143 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 144 {
 145   if (addr + len < addr)
 146     return false;
 147   return bus.load(addr, len, bytes);
 148 }
 149
 150 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 151 {
 152   if (addr + len < addr)
 153     return false;
 154   return bus.store(addr, len, bytes);
 155 }
 156
 157 static std::string dts_compile(const std::string& dts)
 158 {
 159   // Convert the DTS to DTB
 160   int dts_pipe[2];
 161   pid_t dts_pid;
 162
 163   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 164     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 165     exit(1);
 166   }
 167
 168   // Child process to output dts
 169   if (dts_pid == 0) {
 170     close(dts_pipe[0]);
 171     int step, len = dts.length();
 172     const char *buf = dts.c_str();
 173     for (int done = 0; done < len; done += step) {
 174       step = write(dts_pipe[1], buf+done, len-done);
 175       if (step == -1) {
 176         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 177         exit(1);
 178       }
 179     }
 180     close(dts_pipe[1]);
 181     exit(0);
 182   }
 183
 184   pid_t dtb_pid;
 185   int dtb_pipe[2];
 186   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 187     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 188     exit(1);
 189   }
 190
 191   // Child process to output dtb
 192   if (dtb_pid == 0) {
 193     dup2(dts_pipe[0], 0);
 194     dup2(dtb_pipe[1], 1);
 195     close(dts_pipe[0]);
 196     close(dts_pipe[1]);
 197     close(dtb_pipe[0]);
 198     close(dtb_pipe[1]);
 199     execl(DTC, DTC, "-O", "dtb", 0);
 200     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 201     exit(1);
 202   }
 203
 204   close(dts_pipe[1]);
 205   close(dts_pipe[0]);
 206   close(dtb_pipe[1]);
 207
 208   // Read-out dtb
 209   std::stringstream dtb;
 210
 211   int got;
 212   char buf[4096];
 213   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 214     dtb.write(buf, got);
 215   }
 216   if (got == -1) {
 217     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 218     exit(1);
 219   }
 220   close(dtb_pipe[0]);
 221
 222   // Reap children
 223   int status;
 224   waitpid(dts_pid, &status, 0);
 225   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 226     std::cerr << "Child dts process failed" << std::endl;
 227     exit(1);
 228   }
 229   waitpid(dtb_pid, &status, 0);
 230   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 231     std::cerr << "Child dtb process failed" << std::endl;
 232     exit(1);
 233   }
 234
 235   return dtb.str();
 236 }
 237
 238 void sim_t::make_dtb()
 239 {
 240   const int reset_vec_size = 8;
 241
 242   start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
 243
 244   uint32_t reset_vec[reset_vec_size] = {
 245     0x297,                                      // auipc  t0,0x0
 246     0x28593 + (reset_vec_size * 4 << 20),       // addi   a1, t0, &dtb
 247     0xf1402573,                                 // csrr   a0, mhartid
 248     get_core(0)->xlen == 32 ?
 249       0x0182a283u :                             // lw     t0,24(t0)
 250       0x0182b283u,                              // ld     t0,24(t0)
 251     0x28067,                                    // jr     t0
 252     0,
 253     (uint32_t) (start_pc & 0xffffffff),
 254     (uint32_t) (start_pc >> 32)
 255   };
 256
 257   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 258
 259   std::stringstream s;
 260   s << std::dec <<
 261          "/dts-v1/;\n"
 262          "\n"
 263          "/ {\n"
 264          "  #address-cells = <2>;\n"
 265          "  #size-cells = <2>;\n"
 266          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 267          "  model = \"ucbbar,spike-bare\";\n"
 268          "  cpus {\n"
 269          "    #address-cells = <1>;\n"
 270          "    #size-cells = <0>;\n"
 271          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 272   for (size_t i = 0; i < procs.size(); i++) {
 273     s << "    CPU" << i << ": cpu@" << i << " {\n"
 274          "      device_type = \"cpu\";\n"
 275          "      reg = <" << i << ">;\n"
 276          "      status = \"okay\";\n"
 277          "      compatible = \"riscv\";\n"
 278          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 279          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 280          "      clock-frequency = <" << CPU_HZ << ">;\n"
 281          "      CPU" << i << "_intc: interrupt-controller {\n"
 282          "        #interrupt-cells = <1>;\n"
 283          "        interrupt-controller;\n"
 284          "        compatible = \"riscv,cpu-intc\";\n"
 285          "      };\n"
 286          "    };\n";
 287   }
 288   s <<   "  };\n";
 289   for (auto& m : mems) {
 290     s << std::hex <<
 291          "  memory@" << m.first << " {\n"
 292          "    device_type = \"memory\";\n"
 293          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 294                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 295          "  };\n";
 296   }
 297   s <<   "  soc {\n"
 298          "    #address-cells = <2>;\n"
 299          "    #size-cells = <2>;\n"
 300          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 301          "    ranges;\n"
 302          "    clint@" << CLINT_BASE << " {\n"
 303          "      compatible = \"riscv,clint0\";\n"
 304          "      interrupts-extended = <" << std::dec;
 305   for (size_t i = 0; i < procs.size(); i++)
 306     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 307   reg_t clintbs = CLINT_BASE;
 308   reg_t clintsz = CLINT_SIZE;
 309   s << std::hex << ">;\n"
 310          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 311                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 312          "    };\n"
 313          "  };\n"
 314          "  htif {\n"
 315          "    compatible = \"ucb,htif0\";\n"
 316          "  };\n"
 317          "};\n";
 318
 319   dts = s.str();
 320   std::string dtb = dts_compile(dts);
 321
 322   rom.insert(rom.end(), dtb.begin(), dtb.end());
 323   const int align = 0x1000;
 324   rom.resize((rom.size() + align - 1) / align * align);
 325
 326   boot_rom.reset(new rom_device_t(rom));
 327   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 328 }
 329
 330 char* sim_t::addr_to_mem(reg_t addr) {
 331   auto desc = bus.find_device(addr);
 332   if (auto mem = dynamic_cast<mem_t*>(desc.second))
 333     if (addr - desc.first < mem->size())
 334       return mem->contents() + (addr - desc.first);
 335   return NULL;
 336 }
 337
 338 // htif
 339
 340 void sim_t::reset()
 341 {
 342   make_dtb();
 343 }
 344
 345 void sim_t::idle()
 346 {
 347   target.switch_to();
 348 }
 349
 350 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 351 {
 352   assert(len == 8);
 353   auto data = debug_mmu->load_uint64(taddr);
 354   memcpy(dst, &data, sizeof data);
 355 }
 356
 357 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 358 {
 359   assert(len == 8);
 360   uint64_t data;
 361   memcpy(&data, src, sizeof data);
 362   debug_mmu->store_uint64(taddr, data);
 363 }