riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "remote_bitbang.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args,
  29              std::vector<int> const hartids, unsigned progsize)
  30   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
  31     start_pc(start_pc), current_step(0), current_proc(0), debug(false),
  32     remote_bitbang(NULL), debug_module(this, progsize)
  33 {
  34   signal(SIGINT, &handle_signal);
  35
  36   for (auto& x : mems)
  37     bus.add_device(x.first, x.second);
  38
  39   debug_module.add_device(&bus);
  40
  41   debug_mmu = new mmu_t(this, NULL);
  42
  43   if (hartids.size() == 0) {
  44     for (size_t i = 0; i < procs.size(); i++) {
  45       procs[i] = new processor_t(isa, this, i, halted);
  46     }
  47   }
  48   else {
  49     if (hartids.size() != procs.size()) {
  50       std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
  51       exit(1);
  52     }
  53     for (size_t i = 0; i < procs.size(); i++) {
  54       procs[i] = new processor_t(isa, this, hartids[i], halted);
  55     }
  56   }
  57
  58   clint.reset(new clint_t(procs));
  59   bus.add_device(CLINT_BASE, clint.get());
  60 }
  61
  62 sim_t::~sim_t()
  63 {
  64   for (size_t i = 0; i < procs.size(); i++)
  65     delete procs[i];
  66   delete debug_mmu;
  67 }
  68
  69 void sim_thread_main(void* arg)
  70 {
  71   ((sim_t*)arg)->main();
  72 }
  73
  74 void sim_t::main()
  75 {
  76   if (!debug && log)
  77     set_procs_debug(true);
  78
  79   while (!done())
  80   {
  81     if (debug || ctrlc_pressed)
  82       interactive();
  83     else
  84       step(INTERLEAVE);
  85     if (remote_bitbang) {
  86       remote_bitbang->tick();
  87     }
  88   }
  89 }
  90
  91 int sim_t::run()
  92 {
  93   host = context_t::current();
  94   target.init(sim_thread_main, this);
  95   return htif_t::run();
  96 }
  97
  98 void sim_t::step(size_t n)
  99 {
 100   for (size_t i = 0, steps = 0; i < n; i += steps)
 101   {
 102     steps = std::min(n - i, INTERLEAVE - current_step);
 103     procs[current_proc]->step(steps);
 104
 105     current_step += steps;
 106     if (current_step == INTERLEAVE)
 107     {
 108       current_step = 0;
 109       procs[current_proc]->yield_load_reservation();
 110       if (++current_proc == procs.size()) {
 111         current_proc = 0;
 112         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 113       }
 114
 115       host->switch_to();
 116     }
 117   }
 118 }
 119
 120 void sim_t::set_debug(bool value)
 121 {
 122   debug = value;
 123 }
 124
 125 void sim_t::set_log(bool value)
 126 {
 127   log = value;
 128 }
 129
 130 void sim_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133   for (size_t i = 0; i < procs.size(); i++) {
 134     procs[i]->set_histogram(histogram_enabled);
 135   }
 136 }
 137
 138 void sim_t::set_procs_debug(bool value)
 139 {
 140   for (size_t i=0; i< procs.size(); i++)
 141     procs[i]->set_debug(value);
 142 }
 143
 144 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 145 {
 146   if (addr + len < addr)
 147     return false;
 148   return bus.load(addr, len, bytes);
 149 }
 150
 151 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 152 {
 153   if (addr + len < addr)
 154     return false;
 155   return bus.store(addr, len, bytes);
 156 }
 157
 158 static std::string dts_compile(const std::string& dts)
 159 {
 160   // Convert the DTS to DTB
 161   int dts_pipe[2];
 162   pid_t dts_pid;
 163
 164   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 165     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 166     exit(1);
 167   }
 168
 169   // Child process to output dts
 170   if (dts_pid == 0) {
 171     close(dts_pipe[0]);
 172     int step, len = dts.length();
 173     const char *buf = dts.c_str();
 174     for (int done = 0; done < len; done += step) {
 175       step = write(dts_pipe[1], buf+done, len-done);
 176       if (step == -1) {
 177         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 178         exit(1);
 179       }
 180     }
 181     close(dts_pipe[1]);
 182     exit(0);
 183   }
 184
 185   pid_t dtb_pid;
 186   int dtb_pipe[2];
 187   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 188     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 189     exit(1);
 190   }
 191
 192   // Child process to output dtb
 193   if (dtb_pid == 0) {
 194     dup2(dts_pipe[0], 0);
 195     dup2(dtb_pipe[1], 1);
 196     close(dts_pipe[0]);
 197     close(dts_pipe[1]);
 198     close(dtb_pipe[0]);
 199     close(dtb_pipe[1]);
 200     execl(DTC, DTC, "-O", "dtb", 0);
 201     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 202     exit(1);
 203   }
 204
 205   close(dts_pipe[1]);
 206   close(dts_pipe[0]);
 207   close(dtb_pipe[1]);
 208
 209   // Read-out dtb
 210   std::stringstream dtb;
 211
 212   int got;
 213   char buf[4096];
 214   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 215     dtb.write(buf, got);
 216   }
 217   if (got == -1) {
 218     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 219     exit(1);
 220   }
 221   close(dtb_pipe[0]);
 222
 223   // Reap children
 224   int status;
 225   waitpid(dts_pid, &status, 0);
 226   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 227     std::cerr << "Child dts process failed" << std::endl;
 228     exit(1);
 229   }
 230   waitpid(dtb_pid, &status, 0);
 231   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 232     std::cerr << "Child dtb process failed" << std::endl;
 233     exit(1);
 234   }
 235
 236   return dtb.str();
 237 }
 238
 239 void sim_t::make_dtb()
 240 {
 241   const int reset_vec_size = 8;
 242
 243   start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
 244
 245   uint32_t reset_vec[reset_vec_size] = {
 246     0x297,                                      // auipc  t0,0x0
 247     0x28593 + (reset_vec_size * 4 << 20),       // addi   a1, t0, &dtb
 248     0xf1402573,                                 // csrr   a0, mhartid
 249     get_core(0)->xlen == 32 ?
 250       0x0182a283u :                             // lw     t0,24(t0)
 251       0x0182b283u,                              // ld     t0,24(t0)
 252     0x28067,                                    // jr     t0
 253     0,
 254     (uint32_t) (start_pc & 0xffffffff),
 255     (uint32_t) (start_pc >> 32)
 256   };
 257
 258   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 259
 260   std::stringstream s;
 261   s << std::dec <<
 262          "/dts-v1/;\n"
 263          "\n"
 264          "/ {\n"
 265          "  #address-cells = <2>;\n"
 266          "  #size-cells = <2>;\n"
 267          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 268          "  model = \"ucbbar,spike-bare\";\n"
 269          "  cpus {\n"
 270          "    #address-cells = <1>;\n"
 271          "    #size-cells = <0>;\n"
 272          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 273   for (size_t i = 0; i < procs.size(); i++) {
 274     s << "    CPU" << i << ": cpu@" << i << " {\n"
 275          "      device_type = \"cpu\";\n"
 276          "      reg = <" << i << ">;\n"
 277          "      status = \"okay\";\n"
 278          "      compatible = \"riscv\";\n"
 279          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 280          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 281          "      clock-frequency = <" << CPU_HZ << ">;\n"
 282          "      CPU" << i << "_intc: interrupt-controller {\n"
 283          "        #interrupt-cells = <1>;\n"
 284          "        interrupt-controller;\n"
 285          "        compatible = \"riscv,cpu-intc\";\n"
 286          "      };\n"
 287          "    };\n";
 288   }
 289   s <<   "  };\n";
 290   for (auto& m : mems) {
 291     s << std::hex <<
 292          "  memory@" << m.first << " {\n"
 293          "    device_type = \"memory\";\n"
 294          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 295                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 296          "  };\n";
 297   }
 298   s <<   "  soc {\n"
 299          "    #address-cells = <2>;\n"
 300          "    #size-cells = <2>;\n"
 301          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 302          "    ranges;\n"
 303          "    clint@" << CLINT_BASE << " {\n"
 304          "      compatible = \"riscv,clint0\";\n"
 305          "      interrupts-extended = <" << std::dec;
 306   for (size_t i = 0; i < procs.size(); i++)
 307     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 308   reg_t clintbs = CLINT_BASE;
 309   reg_t clintsz = CLINT_SIZE;
 310   s << std::hex << ">;\n"
 311          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 312                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 313          "    };\n"
 314          "  };\n"
 315          "  htif {\n"
 316          "    compatible = \"ucb,htif0\";\n"
 317          "  };\n"
 318          "};\n";
 319
 320   dts = s.str();
 321   std::string dtb = dts_compile(dts);
 322
 323   rom.insert(rom.end(), dtb.begin(), dtb.end());
 324   const int align = 0x1000;
 325   rom.resize((rom.size() + align - 1) / align * align);
 326
 327   boot_rom.reset(new rom_device_t(rom));
 328   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 329 }
 330
 331 char* sim_t::addr_to_mem(reg_t addr) {
 332   auto desc = bus.find_device(addr);
 333   if (auto mem = dynamic_cast<mem_t*>(desc.second))
 334     if (addr - desc.first < mem->size())
 335       return mem->contents() + (addr - desc.first);
 336   return NULL;
 337 }
 338
 339 // htif
 340
 341 void sim_t::reset()
 342 {
 343   make_dtb();
 344 }
 345
 346 void sim_t::idle()
 347 {
 348   target.switch_to();
 349 }
 350
 351 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 352 {
 353   assert(len == 8);
 354   auto data = debug_mmu->load_uint64(taddr);
 355   memcpy(dst, &data, sizeof data);
 356 }
 357
 358 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 359 {
 360   assert(len == 8);
 361   uint64_t data;
 362   memcpy(&data, src, sizeof data);
 363   debug_mmu->store_uint64(taddr, data);
 364 }