riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "gdbserver.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
  27              std::vector<std::pair<reg_t, mem_t*>> mems,
  28              const std::vector<std::string>& args)
  29   : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
  30     start_pc(start_pc),
  31     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  32 {
  33   signal(SIGINT, &handle_signal);
  34
  35   for (auto& x : mems)
  36     bus.add_device(x.first, x.second);
  37
  38   bus.add_device(DEBUG_START, &debug_module);
  39
  40   debug_mmu = new mmu_t(this, NULL);
  41
  42   for (size_t i = 0; i < procs.size(); i++) {
  43     procs[i] = new processor_t(isa, this, i, halted);
  44   }
  45
  46   clint.reset(new clint_t(procs));
  47   bus.add_device(CLINT_BASE, clint.get());
  48 }
  49
  50 sim_t::~sim_t()
  51 {
  52   for (size_t i = 0; i < procs.size(); i++)
  53     delete procs[i];
  54   delete debug_mmu;
  55 }
  56
  57 void sim_thread_main(void* arg)
  58 {
  59   ((sim_t*)arg)->main();
  60 }
  61
  62 void sim_t::main()
  63 {
  64   if (!debug && log)
  65     set_procs_debug(true);
  66
  67   while (!done())
  68   {
  69     if (debug || ctrlc_pressed)
  70       interactive();
  71     else
  72       step(INTERLEAVE);
  73     if (gdbserver) {
  74       gdbserver->handle();
  75     }
  76   }
  77 }
  78
  79 int sim_t::run()
  80 {
  81   host = context_t::current();
  82   target.init(sim_thread_main, this);
  83   return htif_t::run();
  84 }
  85
  86 void sim_t::step(size_t n)
  87 {
  88   for (size_t i = 0, steps = 0; i < n; i += steps)
  89   {
  90     steps = std::min(n - i, INTERLEAVE - current_step);
  91     procs[current_proc]->step(steps);
  92
  93     current_step += steps;
  94     if (current_step == INTERLEAVE)
  95     {
  96       current_step = 0;
  97       procs[current_proc]->yield_load_reservation();
  98       if (++current_proc == procs.size()) {
  99         current_proc = 0;
 100         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 101       }
 102
 103       host->switch_to();
 104     }
 105   }
 106 }
 107
 108 void sim_t::set_debug(bool value)
 109 {
 110   debug = value;
 111 }
 112
 113 void sim_t::set_log(bool value)
 114 {
 115   log = value;
 116 }
 117
 118 void sim_t::set_histogram(bool value)
 119 {
 120   histogram_enabled = value;
 121   for (size_t i = 0; i < procs.size(); i++) {
 122     procs[i]->set_histogram(histogram_enabled);
 123   }
 124 }
 125
 126 void sim_t::set_procs_debug(bool value)
 127 {
 128   for (size_t i=0; i< procs.size(); i++)
 129     procs[i]->set_debug(value);
 130 }
 131
 132 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 133 {
 134   if (addr + len < addr)
 135     return false;
 136   return bus.load(addr, len, bytes);
 137 }
 138
 139 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 140 {
 141   if (addr + len < addr)
 142     return false;
 143   return bus.store(addr, len, bytes);
 144 }
 145
 146 static std::string dts_compile(const std::string& dts)
 147 {
 148   // Convert the DTS to DTB
 149   int dts_pipe[2];
 150   pid_t dts_pid;
 151
 152   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 153     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 154     exit(1);
 155   }
 156
 157   // Child process to output dts
 158   if (dts_pid == 0) {
 159     close(dts_pipe[0]);
 160     int step, len = dts.length();
 161     const char *buf = dts.c_str();
 162     for (int done = 0; done < len; done += step) {
 163       step = write(dts_pipe[1], buf+done, len-done);
 164       if (step == -1) {
 165         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 166         exit(1);
 167       }
 168     }
 169     close(dts_pipe[1]);
 170     exit(0);
 171   }
 172
 173   pid_t dtb_pid;
 174   int dtb_pipe[2];
 175   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 176     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 177     exit(1);
 178   }
 179
 180   // Child process to output dtb
 181   if (dtb_pid == 0) {
 182     dup2(dts_pipe[0], 0);
 183     dup2(dtb_pipe[1], 1);
 184     close(dts_pipe[0]);
 185     close(dts_pipe[1]);
 186     close(dtb_pipe[0]);
 187     close(dtb_pipe[1]);
 188     execl(DTC, DTC, "-O", "dtb", 0);
 189     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 190     exit(1);
 191   }
 192
 193   close(dts_pipe[1]);
 194   close(dts_pipe[0]);
 195   close(dtb_pipe[1]);
 196
 197   // Read-out dtb
 198   std::stringstream dtb;
 199
 200   int got;
 201   char buf[4096];
 202   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 203     dtb.write(buf, got);
 204   }
 205   if (got == -1) {
 206     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 207     exit(1);
 208   }
 209   close(dtb_pipe[0]);
 210
 211   // Reap children
 212   int status;
 213   waitpid(dts_pid, &status, 0);
 214   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 215     std::cerr << "Child dts process failed" << std::endl;
 216     exit(1);
 217   }
 218   waitpid(dtb_pid, &status, 0);
 219   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 220     std::cerr << "Child dtb process failed" << std::endl;
 221     exit(1);
 222   }
 223
 224   return dtb.str();
 225 }
 226
 227 void sim_t::make_dtb()
 228 {
 229   const int reset_vec_size = 8;
 230
 231   start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
 232   reg_t pc_delta = start_pc - DEFAULT_RSTVEC;
 233   reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU);
 234   reg_t pc_delta_lo = pc_delta - pc_delta_hi;
 235   if ((pc_delta_hi >> 31) != 0 && (pc_delta_hi >> 31) != reg_t(-1) >> 31) {
 236     fprintf(stderr, "initial pc %" PRIx64 " out of range\n", pc_delta);
 237     abort();
 238   }
 239
 240   uint32_t reset_vec[reset_vec_size] = {
 241     0x297 + uint32_t(pc_delta_hi),              // auipc t0, &pc
 242     0x597,                                      // auipc a1, &dtb
 243     0x58593 + ((reset_vec_size - 1) * 4 << 20), // addi a1, a1, &dtb
 244     0xf1402573,                                 // csrr a0, mhartid
 245     0x28067 + uint32_t(pc_delta_lo << 20)       // jalr zero, t0, &pc
 246   };
 247
 248   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 249
 250   std::stringstream s;
 251   s << std::dec <<
 252          "/dts-v1/;\n"
 253          "\n"
 254          "/ {\n"
 255          "  #address-cells = <2>;\n"
 256          "  #size-cells = <2>;\n"
 257          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 258          "  model = \"ucbbar,spike-bare\";\n"
 259          "  cpus {\n"
 260          "    #address-cells = <1>;\n"
 261          "    #size-cells = <0>;\n"
 262          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 263   for (size_t i = 0; i < procs.size(); i++) {
 264     s << "    CPU" << i << ": cpu@" << i << " {\n"
 265          "      device_type = \"cpu\";\n"
 266          "      reg = <" << i << ">;\n"
 267          "      status = \"okay\";\n"
 268          "      compatible = \"riscv\";\n"
 269          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 270          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 271          "      clock-frequency = <" << CPU_HZ << ">;\n"
 272          "      CPU" << i << "_intc: interrupt-controller {\n"
 273          "        #interrupt-cells = <1>;\n"
 274          "        interrupt-controller;\n"
 275          "        compatible = \"riscv,cpu-intc\";\n"
 276          "      };\n"
 277          "    };\n";
 278   }
 279   s <<   "  };\n";
 280   for (auto& m : mems) {
 281     s << std::hex <<
 282          "  memory@" << m.first << " {\n"
 283          "    device_type = \"memory\";\n"
 284          "    reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
 285                    " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
 286          "  };\n";
 287   }
 288   s <<   "  soc {\n"
 289          "    #address-cells = <2>;\n"
 290          "    #size-cells = <2>;\n"
 291          "    compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
 292          "    ranges;\n"
 293          "    clint@" << CLINT_BASE << " {\n"
 294          "      compatible = \"riscv,clint0\";\n"
 295          "      interrupts-extended = <" << std::dec;
 296   for (size_t i = 0; i < procs.size(); i++)
 297     s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
 298   reg_t clintbs = CLINT_BASE;
 299   reg_t clintsz = CLINT_SIZE;
 300   s << std::hex << ">;\n"
 301          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 302                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 303          "    };\n"
 304          "  };\n"
 305          "};\n";
 306
 307   dts = s.str();
 308   std::string dtb = dts_compile(dts);
 309
 310   rom.insert(rom.end(), dtb.begin(), dtb.end());
 311   const int align = 0x1000;
 312   rom.resize((rom.size() + align - 1) / align * align);
 313
 314   boot_rom.reset(new rom_device_t(rom));
 315   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 316 }
 317
 318 char* sim_t::addr_to_mem(reg_t addr) {
 319   auto desc = bus.find_device(addr);
 320   if (auto mem = dynamic_cast<mem_t*>(desc.device))
 321     return mem->contents() + (addr - desc.base);
 322   return NULL;
 323 }
 324
 325 // htif
 326
 327 void sim_t::reset()
 328 {
 329   make_dtb();
 330 }
 331
 332 void sim_t::idle()
 333 {
 334   target.switch_to();
 335 }
 336
 337 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 338 {
 339   assert(len == 8);
 340   auto data = debug_mmu->load_uint64(taddr);
 341   memcpy(dst, &data, sizeof data);
 342 }
 343
 344 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 345 {
 346   assert(len == 8);
 347   uint64_t data;
 348   memcpy(&data, src, sizeof data);
 349   debug_mmu->store_uint64(taddr, data);
 350 }