riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "gdbserver.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  27              const std::vector<std::string>& args)
  28   : htif_t(args), procs(std::max(nprocs, size_t(1))),
  29     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  30 {
  31   signal(SIGINT, &handle_signal);
  32   // allocate target machine's memory, shrinking it as necessary
  33   // until the allocation succeeds
  34   size_t memsz0 = (size_t)mem_mb << 20;
  35   size_t quantum = 1L << 20;
  36   if (memsz0 == 0)
  37     memsz0 = (size_t)2048 << 20;
  38
  39   memsz = memsz0;
  40   while ((mem = (char*)calloc(1, memsz)) == NULL)
  41     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  42
  43   if (memsz != memsz0)
  44     fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
  45             memsz, memsz0);
  46
  47   bus.add_device(DEBUG_START, &debug_module);
  48
  49   debug_mmu = new mmu_t(this, NULL);
  50
  51   for (size_t i = 0; i < procs.size(); i++) {
  52     procs[i] = new processor_t(isa, this, i, halted);
  53   }
  54
  55   clint.reset(new clint_t(procs));
  56   bus.add_device(CLINT_BASE, clint.get());
  57
  58   make_dtb();
  59 }
  60
  61 sim_t::~sim_t()
  62 {
  63   for (size_t i = 0; i < procs.size(); i++)
  64     delete procs[i];
  65   delete debug_mmu;
  66   free(mem);
  67 }
  68
  69 void sim_thread_main(void* arg)
  70 {
  71   ((sim_t*)arg)->main();
  72 }
  73
  74 void sim_t::main()
  75 {
  76   if (!debug && log)
  77     set_procs_debug(true);
  78
  79   while (!done())
  80   {
  81     if (debug || ctrlc_pressed)
  82       interactive();
  83     else
  84       step(INTERLEAVE);
  85     if (gdbserver) {
  86       gdbserver->handle();
  87     }
  88   }
  89 }
  90
  91 int sim_t::run()
  92 {
  93   host = context_t::current();
  94   target.init(sim_thread_main, this);
  95   return htif_t::run();
  96 }
  97
  98 void sim_t::step(size_t n)
  99 {
 100   for (size_t i = 0, steps = 0; i < n; i += steps)
 101   {
 102     steps = std::min(n - i, INTERLEAVE - current_step);
 103     procs[current_proc]->step(steps);
 104
 105     current_step += steps;
 106     if (current_step == INTERLEAVE)
 107     {
 108       current_step = 0;
 109       procs[current_proc]->yield_load_reservation();
 110       if (++current_proc == procs.size()) {
 111         current_proc = 0;
 112         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 113       }
 114
 115       host->switch_to();
 116     }
 117   }
 118 }
 119
 120 void sim_t::set_debug(bool value)
 121 {
 122   debug = value;
 123 }
 124
 125 void sim_t::set_log(bool value)
 126 {
 127   log = value;
 128 }
 129
 130 void sim_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133   for (size_t i = 0; i < procs.size(); i++) {
 134     procs[i]->set_histogram(histogram_enabled);
 135   }
 136 }
 137
 138 void sim_t::set_procs_debug(bool value)
 139 {
 140   for (size_t i=0; i< procs.size(); i++)
 141     procs[i]->set_debug(value);
 142 }
 143
 144 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 145 {
 146   if (addr + len < addr)
 147     return false;
 148   return bus.load(addr, len, bytes);
 149 }
 150
 151 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 152 {
 153   if (addr + len < addr)
 154     return false;
 155   return bus.store(addr, len, bytes);
 156 }
 157
 158 static std::string dts_compile(const std::string& dts)
 159 {
 160   // Convert the DTS to DTB
 161   int dts_pipe[2];
 162   pid_t dts_pid;
 163
 164   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 165     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 166     exit(1);
 167   }
 168
 169   // Child process to output dts
 170   if (dts_pid == 0) {
 171     close(dts_pipe[0]);
 172     int step, len = dts.length();
 173     const char *buf = dts.c_str();
 174     for (int done = 0; done < len; done += step) {
 175       step = write(dts_pipe[1], buf+done, len-done);
 176       if (step == -1) {
 177         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 178         exit(1);
 179       }
 180     }
 181     close(dts_pipe[1]);
 182     exit(0);
 183   }
 184
 185   pid_t dtb_pid;
 186   int dtb_pipe[2];
 187   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 188     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 189     exit(1);
 190   }
 191
 192   // Child process to output dtb
 193   if (dtb_pid == 0) {
 194     dup2(dts_pipe[0], 0);
 195     dup2(dtb_pipe[1], 1);
 196     close(dts_pipe[0]);
 197     close(dts_pipe[1]);
 198     close(dtb_pipe[0]);
 199     close(dtb_pipe[1]);
 200     execl(DTC, DTC, "-O", "dtb", 0);
 201     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 202     exit(1);
 203   }
 204
 205   close(dts_pipe[1]);
 206   close(dts_pipe[0]);
 207   close(dtb_pipe[1]);
 208
 209   // Read-out dtb
 210   std::stringstream dtb;
 211
 212   int got;
 213   char buf[4096];
 214   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 215     dtb.write(buf, got);
 216   }
 217   if (got == -1) {
 218     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 219     exit(1);
 220   }
 221   close(dtb_pipe[0]);
 222
 223   // Reap children
 224   int status;
 225   waitpid(dts_pid, &status, 0);
 226   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 227     std::cerr << "Child dts process failed" << std::endl;
 228     exit(1);
 229   }
 230   waitpid(dtb_pid, &status, 0);
 231   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 232     std::cerr << "Child dtb process failed" << std::endl;
 233     exit(1);
 234   }
 235
 236   return dtb.str();
 237 }
 238
 239 void sim_t::make_dtb()
 240 {
 241   uint32_t reset_vec[] = {
 242     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
 243     0x597,                              // auipc a1, 0
 244     0x58593,                            // addi a1, a1, 0
 245     0xf1402573,                         // csrr a0,mhartid
 246     0x00028067                          // jalr zero, t0, 0 (jump straight to DRAM_BASE)
 247   };
 248   reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
 249
 250   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 251
 252   std::stringstream s;
 253   s << std::dec <<
 254          "/dts-v1/;\n"
 255          "\n"
 256          "/ {\n"
 257          "  #address-cells = <2>;\n"
 258          "  #size-cells = <2>;\n"
 259          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 260          "  model = \"ucbbar,spike-bare\";\n"
 261          "  cpus {\n"
 262          "    #address-cells = <1>;\n"
 263          "    #size-cells = <0>;\n"
 264          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 265   for (size_t i = 0; i < procs.size(); i++) {
 266     s << "    CPU" << i << ": cpu@" << i << " {\n"
 267          "      device_type = \"cpu\";\n"
 268          "      reg = <" << i << ">;\n"
 269          "      status = \"okay\";\n"
 270          "      compatible = \"riscv\";\n"
 271          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 272          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 273          "      clock-frequency = <" << CPU_HZ << ">;\n"
 274          "      interrupt-controller;\n"
 275          "      #interrupt-cells = <1>;\n"
 276          "    };\n";
 277   }
 278   reg_t membs = DRAM_BASE;
 279   s << std::hex <<
 280          "  };\n"
 281          "  memory@" << DRAM_BASE << " {\n"
 282          "    device_type = \"memory\";\n"
 283          "    reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
 284                    " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
 285          "  };\n"
 286          "  soc {\n"
 287          "    #address-cells = <2>;\n"
 288          "    #size-cells = <2>;\n"
 289          "    compatible = \"ucbbar,spike-bare-soc\";\n"
 290          "    ranges;\n"
 291          "    clint@" << CLINT_BASE << " {\n"
 292          "      compatible = \"riscv,clint0\";\n"
 293          "      interrupts-extended = <" << std::dec;
 294   for (size_t i = 0; i < procs.size(); i++)
 295     s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
 296   reg_t clintbs = CLINT_BASE;
 297   reg_t clintsz = CLINT_SIZE;
 298   s << std::hex << ">;\n"
 299          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
 300                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
 301          "    };\n"
 302          "  };\n"
 303          "};\n";
 304
 305   dts = s.str();
 306   std::string dtb = dts_compile(dts);
 307
 308   rom.insert(rom.end(), dtb.begin(), dtb.end());
 309   const int align = 0x1000;
 310   rom.resize((rom.size() + align - 1) / align * align);
 311
 312   boot_rom.reset(new rom_device_t(rom));
 313   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 314 }
 315
 316 // htif
 317
 318 void sim_t::idle()
 319 {
 320   target.switch_to();
 321 }
 322
 323 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 324 {
 325   assert(len == 8);
 326   auto data = debug_mmu->load_uint64(taddr);
 327   memcpy(dst, &data, sizeof data);
 328 }
 329
 330 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 331 {
 332   assert(len == 8);
 333   uint64_t data;
 334   memcpy(&data, src, sizeof data);
 335   debug_mmu->store_uint64(taddr, data);
 336 }