riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "gdbserver.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13
  14 volatile bool ctrlc_pressed = false;
  15 static void handle_signal(int sig)
  16 {
  17   if (ctrlc_pressed)
  18     exit(-1);
  19   ctrlc_pressed = true;
  20   signal(sig, &handle_signal);
  21 }
  22
  23 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  24              const std::vector<std::string>& args)
  25   : htif_t(args), procs(std::max(nprocs, size_t(1))),
  26     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  27 {
  28   signal(SIGINT, &handle_signal);
  29   // allocate target machine's memory, shrinking it as necessary
  30   // until the allocation succeeds
  31   size_t memsz0 = (size_t)mem_mb << 20;
  32   size_t quantum = 1L << 20;
  33   if (memsz0 == 0)
  34     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  35
  36   memsz = memsz0;
  37   while ((mem = (char*)calloc(1, memsz)) == NULL)
  38     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  39
  40   if (memsz != memsz0)
  41     fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
  42             memsz, memsz0);
  43
  44   bus.add_device(DEBUG_START, &debug_module);
  45
  46   debug_mmu = new mmu_t(this, NULL);
  47
  48   for (size_t i = 0; i < procs.size(); i++) {
  49     procs[i] = new processor_t(isa, this, i, halted);
  50   }
  51
  52   rtc.reset(new rtc_t(procs));
  53   make_config_string();
  54 }
  55
  56 sim_t::~sim_t()
  57 {
  58   for (size_t i = 0; i < procs.size(); i++)
  59     delete procs[i];
  60   delete debug_mmu;
  61   free(mem);
  62 }
  63
  64 void sim_thread_main(void* arg)
  65 {
  66   ((sim_t*)arg)->main();
  67 }
  68
  69 void sim_t::main()
  70 {
  71   if (!debug && log)
  72     set_procs_debug(true);
  73
  74   while (!done())
  75   {
  76     if (debug || ctrlc_pressed)
  77       interactive();
  78     else
  79       step(INTERLEAVE);
  80     if (gdbserver) {
  81       gdbserver->handle();
  82     }
  83   }
  84 }
  85
  86 int sim_t::run()
  87 {
  88   host = context_t::current();
  89   target.init(sim_thread_main, this);
  90   return htif_t::run();
  91 }
  92
  93 void sim_t::step(size_t n)
  94 {
  95   for (size_t i = 0, steps = 0; i < n; i += steps)
  96   {
  97     steps = std::min(n - i, INTERLEAVE - current_step);
  98     procs[current_proc]->step(steps);
  99
 100     current_step += steps;
 101     if (current_step == INTERLEAVE)
 102     {
 103       current_step = 0;
 104       procs[current_proc]->yield_load_reservation();
 105       if (++current_proc == procs.size()) {
 106         current_proc = 0;
 107         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 108       }
 109
 110       host->switch_to();
 111     }
 112   }
 113 }
 114
 115 void sim_t::set_debug(bool value)
 116 {
 117   debug = value;
 118 }
 119
 120 void sim_t::set_log(bool value)
 121 {
 122   log = value;
 123 }
 124
 125 void sim_t::set_histogram(bool value)
 126 {
 127   histogram_enabled = value;
 128   for (size_t i = 0; i < procs.size(); i++) {
 129     procs[i]->set_histogram(histogram_enabled);
 130   }
 131 }
 132
 133 void sim_t::set_procs_debug(bool value)
 134 {
 135   for (size_t i=0; i< procs.size(); i++)
 136     procs[i]->set_debug(value);
 137 }
 138
 139 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 140 {
 141   if (addr + len < addr)
 142     return false;
 143   return bus.load(addr, len, bytes);
 144 }
 145
 146 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 147 {
 148   if (addr + len < addr)
 149     return false;
 150   return bus.store(addr, len, bytes);
 151 }
 152
 153 void sim_t::make_config_string()
 154 {
 155   reg_t rtc_addr = EXT_IO_BASE;
 156   bus.add_device(rtc_addr, rtc.get());
 157
 158   const int align = 0x1000;
 159   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 160   reg_t cpu_size = align;
 161
 162   uint32_t reset_vec[8] = {
 163     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 164     0x00028067,                         //   jump straight to DRAM_BASE
 165     0x00000000,                         // reserved
 166     0,                                  // config string pointer
 167     0, 0, 0, 0                          // trap vector
 168   };
 169   reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 170
 171   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 172
 173   std::stringstream s;
 174   s << std::dec <<
 175          "/dts-v1/;\n"
 176          "\n"
 177          "/ {\n"
 178          "  #address-cells = <2>;\n"
 179          "  #size-cells = <2>;\n"
 180          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 181          "  model = \"ucbbar,spike-bare\";\n"
 182          "  cpus {\n"
 183          "    #address-cells = <1>;\n"
 184          "    #size-cells = <0>;\n"
 185          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 186   for (size_t i = 0; i < procs.size(); i++) {
 187     s << "    CPU" << i << ": cpu@" << i << " {\n"
 188          "      device_type = \"cpu\";\n"
 189          "      reg = <" << i << ">;\n"
 190          "      status = \"okay\";\n"
 191          "      compatible = \"riscv\";\n"
 192          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 193          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 194          "      clock-frequency = <" << CPU_HZ << ">;\n"
 195          "    };\n";
 196   }
 197   reg_t membs = DRAM_BASE;
 198   s << std::hex <<
 199          "  };\n"
 200          "  memory@" << DRAM_BASE << " {\n"
 201          "    device_type = \"memory\";\n"
 202          "    reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
 203                    " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
 204          "  };\n"
 205          "  soc {\n"
 206          "    #address-cells = <2>;\n"
 207          "    #size-cells = <2>;\n"
 208          "    compatible = \"ucbbar,spike-bare-soc\";\n"
 209          "    ranges;\n"
 210          "    clint@" << rtc_addr << " {\n"
 211          "      compatible = \"riscv,clint0\";\n"
 212          "      interrupts-extended = <" << std::dec;
 213   for (size_t i = 0; i < procs.size(); i++)
 214     s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
 215   s << std::hex << ">;\n"
 216          "      reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
 217                      " 0x0 0x10000>;\n"
 218          "    };\n"
 219          "  };\n"
 220          "};\n";
 221
 222   config_string = s.str();
 223   rom.insert(rom.end(), config_string.begin(), config_string.end());
 224   rom.resize((rom.size() / align + 1) * align);
 225
 226   boot_rom.reset(new rom_device_t(rom));
 227   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 228 }
 229
 230 // htif
 231
 232 void sim_t::idle()
 233 {
 234   target.switch_to();
 235 }
 236
 237 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 238 {
 239   assert(len == 8);
 240   auto data = debug_mmu->load_uint64(taddr);
 241   memcpy(dst, &data, sizeof data);
 242 }
 243
 244 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 245 {
 246   assert(len == 8);
 247   uint64_t data;
 248   memcpy(&data, src, sizeof data);
 249   debug_mmu->store_uint64(taddr, data);
 250 }