riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13
  14 volatile bool ctrlc_pressed = false;
  15 static void handle_signal(int sig)
  16 {
  17   if (ctrlc_pressed)
  18     exit(-1);
  19   ctrlc_pressed = true;
  20   signal(sig, &handle_signal);
  21 }
  22
  23 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  24              const std::vector<std::string>& args)
  25   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  26     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  27 {
  28   signal(SIGINT, &handle_signal);
  29   // allocate target machine's memory, shrinking it as necessary
  30   // until the allocation succeeds
  31   size_t memsz0 = (size_t)mem_mb << 20;
  32   size_t quantum = 1L << 20;
  33   if (memsz0 == 0)
  34     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  35
  36   memsz = memsz0;
  37   while ((mem = (char*)calloc(1, memsz)) == NULL)
  38     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  39
  40   if (memsz != memsz0)
  41     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  42             (unsigned long)memsz, (unsigned long)memsz0);
  43
  44   /* Copy Debug ROM into the end of the allocated block, because we surely
  45    * didn't succeed in allocating 0xfffffffff800 bytes. */
  46   /* TODO: Once everything uses the new memory map, just put this at the
  47    * address that it actually belongs at. */
  48   memcpy(mem + memsz - DEBUG_SIZE + DEBUG_ROM_START - DEBUG_START,
  49           debug_rom_raw, debug_rom_raw_len);
  50
  51   debug_mmu = new mmu_t(this, NULL);
  52
  53   for (size_t i = 0; i < procs.size(); i++) {
  54     procs[i] = new processor_t(isa, this, i);
  55     if (halted)
  56       procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
  57   }
  58
  59   rtc.reset(new rtc_t(procs));
  60   make_config_string();
  61 }
  62
  63 sim_t::~sim_t()
  64 {
  65   for (size_t i = 0; i < procs.size(); i++)
  66     delete procs[i];
  67   delete debug_mmu;
  68   free(mem);
  69 }
  70
  71 int sim_t::run()
  72 {
  73   if (!debug && log)
  74     set_procs_debug(true);
  75   while (htif->tick())
  76   {
  77     if (debug || ctrlc_pressed)
  78       interactive();
  79     else
  80       step(INTERLEAVE);
  81     if (gdbserver) {
  82         gdbserver->handle();
  83     }
  84   }
  85   return htif->exit_code();
  86 }
  87
  88 void sim_t::step(size_t n)
  89 {
  90   for (size_t i = 0, steps = 0; i < n; i += steps)
  91   {
  92     steps = std::min(n - i, INTERLEAVE - current_step);
  93     procs[current_proc]->step(steps);
  94
  95     current_step += steps;
  96     if (current_step == INTERLEAVE)
  97     {
  98       current_step = 0;
  99       procs[current_proc]->yield_load_reservation();
 100       if (++current_proc == procs.size()) {
 101         current_proc = 0;
 102         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 103       }
 104
 105       htif->tick();
 106     }
 107   }
 108 }
 109
 110 bool sim_t::running()
 111 {
 112   for (size_t i = 0; i < procs.size(); i++)
 113     if (procs[i]->running())
 114       return true;
 115   return false;
 116 }
 117
 118 void sim_t::set_debug(bool value)
 119 {
 120   debug = value;
 121 }
 122
 123 void sim_t::set_log(bool value)
 124 {
 125   log = value;
 126 }
 127
 128 void sim_t::set_histogram(bool value)
 129 {
 130   histogram_enabled = value;
 131   for (size_t i = 0; i < procs.size(); i++) {
 132     procs[i]->set_histogram(histogram_enabled);
 133   }
 134 }
 135
 136 void sim_t::set_procs_debug(bool value)
 137 {
 138   for (size_t i=0; i< procs.size(); i++)
 139     procs[i]->set_debug(value);
 140 }
 141
 142 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 143 {
 144   if (addr + len < addr)
 145     return false;
 146   return bus.load(addr, len, bytes);
 147 }
 148
 149 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 150 {
 151   if (addr + len < addr)
 152     return false;
 153   return bus.store(addr, len, bytes);
 154 }
 155
 156 void sim_t::make_config_string()
 157 {
 158   reg_t rtc_addr = EXT_IO_BASE;
 159   bus.add_device(rtc_addr, rtc.get());
 160
 161   const int align = 0x1000;
 162   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 163   reg_t cpu_size = align;
 164
 165   uint32_t reset_vec[8] = {
 166     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 167     0x00028067,                         //   jump straight to DRAM_BASE
 168     0x00000000,                         // reserved
 169     0,                                  // config string pointer
 170     0, 0, 0, 0                          // trap vector
 171   };
 172   reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 173
 174   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 175
 176   std::stringstream s;
 177   s << std::hex <<
 178         "platform {\n"
 179         "  vendor ucb;\n"
 180         "  arch spike;\n"
 181         "};\n"
 182         "rtc {\n"
 183         "  addr 0x" << rtc_addr << ";\n"
 184         "};\n"
 185         "ram {\n"
 186         "  0 {\n"
 187         "    addr 0x" << DRAM_BASE << ";\n"
 188         "    size 0x" << memsz << ";\n"
 189         "  };\n"
 190         "};\n"
 191         "core {\n";
 192   for (size_t i = 0; i < procs.size(); i++) {
 193     s <<
 194         "  " << i << " {\n"
 195         "    " << "0 {\n" << // hart 0 on core i
 196         "      isa " << procs[i]->isa_string << ";\n"
 197         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 198         "      ipi 0x" << cpu_addr << ";\n"
 199         "    };\n"
 200         "  };\n";
 201     bus.add_device(cpu_addr, procs[i]);
 202     cpu_addr += cpu_size;
 203   }
 204   s <<  "};\n";
 205
 206   config_string = s.str();
 207   rom.insert(rom.end(), config_string.begin(), config_string.end());
 208   rom.resize((rom.size() / align + 1) * align);
 209
 210   boot_rom.reset(new rom_device_t(rom));
 211   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 212 }