riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "htif.h"
   5 #include <map>
   6 #include <iostream>
   7 #include <sstream>
   8 #include <climits>
   9 #include <cstdlib>
  10 #include <cassert>
  11 #include <signal.h>
  12
  13 volatile bool ctrlc_pressed = false;
  14 static void handle_signal(int sig)
  15 {
  16   if (ctrlc_pressed)
  17     exit(-1);
  18   ctrlc_pressed = true;
  19   signal(sig, &handle_signal);
  20 }
  21
  22 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
  23              const std::vector<std::string>& args)
  24   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  25     current_step(0), current_proc(0), debug(false)
  26 {
  27   signal(SIGINT, &handle_signal);
  28   // allocate target machine's memory, shrinking it as necessary
  29   // until the allocation succeeds
  30   size_t memsz0 = (size_t)mem_mb << 20;
  31   size_t quantum = 1L << 20;
  32   if (memsz0 == 0)
  33     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  34
  35   memsz = memsz0;
  36   while ((mem = (char*)calloc(1, memsz)) == NULL)
  37     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  38
  39   if (memsz != memsz0)
  40     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  41             (unsigned long)memsz, (unsigned long)memsz0);
  42
  43   debug_mmu = new mmu_t(mem, memsz);
  44
  45   for (size_t i = 0; i < procs.size(); i++)
  46     procs[i] = new processor_t(isa, this, i);
  47
  48   rtc.reset(new rtc_t(procs));
  49   make_config_string();
  50 }
  51
  52 sim_t::~sim_t()
  53 {
  54   for (size_t i = 0; i < procs.size(); i++)
  55     delete procs[i];
  56   delete debug_mmu;
  57   free(mem);
  58 }
  59
  60 reg_t sim_t::get_scr(int which)
  61 {
  62   switch (which)
  63   {
  64     case 0: return procs.size();
  65     case 1: return memsz >> 20;
  66     default: return -1;
  67   }
  68 }
  69
  70 int sim_t::run()
  71 {
  72   if (!debug && log)
  73     set_procs_debug(true);
  74   while (htif->tick())
  75   {
  76     if (debug || ctrlc_pressed)
  77       interactive();
  78     else
  79       step(INTERLEAVE);
  80   }
  81   return htif->exit_code();
  82 }
  83
  84 void sim_t::step(size_t n)
  85 {
  86   for (size_t i = 0, steps = 0; i < n; i += steps)
  87   {
  88     steps = std::min(n - i, INTERLEAVE - current_step);
  89     procs[current_proc]->step(steps);
  90
  91     current_step += steps;
  92     if (current_step == INTERLEAVE)
  93     {
  94       current_step = 0;
  95       procs[current_proc]->yield_load_reservation();
  96       if (++current_proc == procs.size()) {
  97         current_proc = 0;
  98         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
  99       }
 100
 101       htif->tick();
 102     }
 103   }
 104 }
 105
 106 bool sim_t::running()
 107 {
 108   for (size_t i = 0; i < procs.size(); i++)
 109     if (procs[i]->running())
 110       return true;
 111   return false;
 112 }
 113
 114 void sim_t::stop()
 115 {
 116   procs[0]->state.tohost = 1;
 117   while (htif->tick())
 118     ;
 119 }
 120
 121 void sim_t::set_debug(bool value)
 122 {
 123   debug = value;
 124 }
 125
 126 void sim_t::set_log(bool value)
 127 {
 128   log = value;
 129 }
 130
 131 void sim_t::set_histogram(bool value)
 132 {
 133   histogram_enabled = value;
 134   for (size_t i = 0; i < procs.size(); i++) {
 135     procs[i]->set_histogram(histogram_enabled);
 136   }
 137 }
 138
 139 void sim_t::set_procs_debug(bool value)
 140 {
 141   for (size_t i=0; i< procs.size(); i++)
 142     procs[i]->set_debug(value);
 143 }
 144
 145 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 146 {
 147   if (addr + len < addr)
 148     return false;
 149   return bus.load(addr, len, bytes);
 150 }
 151
 152 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 153 {
 154   if (addr + len < addr)
 155     return false;
 156   return bus.store(addr, len, bytes);
 157 }
 158
 159 void sim_t::make_config_string()
 160 {
 161   size_t csr_size = NCSR * 16 /* RV128 */;
 162   size_t device_tree_addr = memsz;
 163   size_t cpu_addr = memsz + csr_size;
 164
 165   reg_t rtc_addr = memsz;
 166   bus.add_device(rtc_addr, rtc.get());
 167   config_string_addr = rtc_addr + rtc->size();
 168
 169   std::stringstream s;
 170   s << std::hex <<
 171         "platform {\n"
 172         "  vendor ucb;\n"
 173         "  arch spike;\n"
 174         "};\n"
 175         "rtc {\n"
 176         "  addr 0x" << rtc_addr << ";\n"
 177         "};\n"
 178         "ram {\n"
 179         "  0 {\n"
 180         "    addr 0;\n"
 181         "    size 0x" << memsz << ";\n"
 182         "  };\n"
 183         "};\n"
 184         "core {\n";
 185   for (size_t i = 0; i < procs.size(); i++) {
 186     s <<
 187         "  " << i << " {\n"
 188         "    " << "0 {\n" << // hart 0 on core i
 189         "      isa " << procs[i]->isa_string << ";\n"
 190         "      addr 0x" << cpu_addr << ";\n"
 191         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 192         "    };\n"
 193         "  };\n";
 194     bus.add_device(cpu_addr, procs[i]);
 195     cpu_addr += csr_size;
 196   }
 197   s <<  "};\n";
 198
 199   std::string str = s.str();
 200   std::vector<char> vec(str.begin(), str.end());
 201   vec.push_back(0);
 202   assert(vec.size() <= csr_size);
 203   config_string.reset(new rom_device_t(vec));
 204   bus.add_device(config_string_addr, config_string.get());
 205 }