riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "htif.h"
   5 #include <map>
   6 #include <iostream>
   7 #include <climits>
   8 #include <cstdlib>
   9 #include <cassert>
  10 #include <signal.h>
  11
  12 volatile bool ctrlc_pressed = false;
  13 static void handle_signal(int sig)
  14 {
  15   if (ctrlc_pressed)
  16     exit(-1);
  17   ctrlc_pressed = true;
  18   signal(sig, &handle_signal);
  19 }
  20
  21 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
  22              const std::vector<std::string>& args)
  23   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  24     rtc(0), current_step(0), current_proc(0), debug(false)
  25 {
  26   signal(SIGINT, &handle_signal);
  27   // allocate target machine's memory, shrinking it as necessary
  28   // until the allocation succeeds
  29   size_t memsz0 = (size_t)mem_mb << 20;
  30   size_t quantum = 1L << 20;
  31   if (memsz0 == 0)
  32     memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30);
  33
  34   memsz = memsz0;
  35   while ((mem = (char*)calloc(1, memsz)) == NULL)
  36     memsz = memsz*10/11/quantum*quantum;
  37
  38   if (memsz != memsz0)
  39     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  40             (unsigned long)memsz, (unsigned long)memsz0);
  41
  42   debug_mmu = new mmu_t(mem, memsz);
  43
  44   for (size_t i = 0; i < procs.size(); i++)
  45     procs[i] = new processor_t(isa, this, i);
  46 }
  47
  48 sim_t::~sim_t()
  49 {
  50   for (size_t i = 0; i < procs.size(); i++)
  51     delete procs[i];
  52   delete debug_mmu;
  53   free(mem);
  54 }
  55
  56 void sim_t::send_ipi(reg_t who)
  57 {
  58   if (who < procs.size())
  59     procs[who]->deliver_ipi();
  60 }
  61
  62 reg_t sim_t::get_scr(int which)
  63 {
  64   switch (which)
  65   {
  66     case 0: return procs.size();
  67     case 1: return memsz >> 20;
  68     default: return -1;
  69   }
  70 }
  71
  72 int sim_t::run()
  73 {
  74   if (!debug && log)
  75     set_procs_debug(true);
  76   while (htif->tick())
  77   {
  78     if (debug || ctrlc_pressed)
  79       interactive();
  80     else
  81       step(INTERLEAVE);
  82   }
  83   return htif->exit_code();
  84 }
  85
  86 void sim_t::step(size_t n)
  87 {
  88   for (size_t i = 0, steps = 0; i < n; i += steps)
  89   {
  90     steps = std::min(n - i, INTERLEAVE - current_step);
  91     procs[current_proc]->step(steps);
  92
  93     current_step += steps;
  94     if (current_step == INTERLEAVE)
  95     {
  96       current_step = 0;
  97       procs[current_proc]->yield_load_reservation();
  98       if (++current_proc == procs.size()) {
  99         current_proc = 0;
 100         rtc += INTERLEAVE / INSNS_PER_RTC_TICK;
 101       }
 102
 103       htif->tick();
 104     }
 105   }
 106 }
 107
 108 bool sim_t::running()
 109 {
 110   for (size_t i = 0; i < procs.size(); i++)
 111     if (procs[i]->running())
 112       return true;
 113   return false;
 114 }
 115
 116 void sim_t::stop()
 117 {
 118   procs[0]->state.tohost = 1;
 119   while (htif->tick())
 120     ;
 121 }
 122
 123 void sim_t::set_debug(bool value)
 124 {
 125   debug = value;
 126 }
 127
 128 void sim_t::set_log(bool value)
 129 {
 130   log = value;
 131 }
 132
 133 void sim_t::set_histogram(bool value)
 134 {
 135   histogram_enabled = value;
 136   for (size_t i = 0; i < procs.size(); i++) {
 137     procs[i]->set_histogram(histogram_enabled);
 138   }
 139 }
 140
 141 void sim_t::set_procs_debug(bool value)
 142 {
 143   for (size_t i=0; i< procs.size(); i++)
 144     procs[i]->set_debug(value);
 145 }
 146