riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13
  14 volatile bool ctrlc_pressed = false;
  15 static void handle_signal(int sig)
  16 {
  17   if (ctrlc_pressed)
  18     exit(-1);
  19   ctrlc_pressed = true;
  20   signal(sig, &handle_signal);
  21 }
  22
  23 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
  24              const std::vector<std::string>& args)
  25   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  26     current_step(0), current_proc(0), debug(false)
  27 {
  28   signal(SIGINT, &handle_signal);
  29   // allocate target machine's memory, shrinking it as necessary
  30   // until the allocation succeeds
  31   size_t memsz0 = (size_t)mem_mb << 20;
  32   size_t quantum = 1L << 20;
  33   if (memsz0 == 0)
  34     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  35
  36   memsz = memsz0;
  37   while ((mem = (char*)calloc(1, memsz)) == NULL)
  38     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  39
  40   if (memsz != memsz0)
  41     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  42             (unsigned long)memsz, (unsigned long)memsz0);
  43
  44   debug_mmu = new mmu_t(this, NULL);
  45
  46   for (size_t i = 0; i < procs.size(); i++)
  47     procs[i] = new processor_t(isa, this, i);
  48
  49   rtc.reset(new rtc_t(procs));
  50   make_config_string();
  51 }
  52
  53 sim_t::~sim_t()
  54 {
  55   for (size_t i = 0; i < procs.size(); i++)
  56     delete procs[i];
  57   delete debug_mmu;
  58   free(mem);
  59 }
  60
  61 reg_t sim_t::get_scr(int which)
  62 {
  63   switch (which)
  64   {
  65     case 0: return procs.size();
  66     case 1: return memsz >> 20;
  67     default: return -1;
  68   }
  69 }
  70
  71 int sim_t::run()
  72 {
  73   if (!debug && log)
  74     set_procs_debug(true);
  75   while (htif->tick())
  76   {
  77     if (debug || ctrlc_pressed)
  78       interactive();
  79     else
  80       step(INTERLEAVE);
  81   }
  82   return htif->exit_code();
  83 }
  84
  85 void sim_t::step(size_t n)
  86 {
  87   for (size_t i = 0, steps = 0; i < n; i += steps)
  88   {
  89     steps = std::min(n - i, INTERLEAVE - current_step);
  90     procs[current_proc]->step(steps);
  91
  92     current_step += steps;
  93     if (current_step == INTERLEAVE)
  94     {
  95       current_step = 0;
  96       procs[current_proc]->yield_load_reservation();
  97       if (++current_proc == procs.size()) {
  98         current_proc = 0;
  99         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 100       }
 101
 102       htif->tick();
 103     }
 104   }
 105 }
 106
 107 bool sim_t::running()
 108 {
 109   for (size_t i = 0; i < procs.size(); i++)
 110     if (procs[i]->running())
 111       return true;
 112   return false;
 113 }
 114
 115 void sim_t::stop()
 116 {
 117   procs[0]->state.tohost = 1;
 118   while (htif->tick())
 119     ;
 120 }
 121
 122 void sim_t::set_debug(bool value)
 123 {
 124   debug = value;
 125 }
 126
 127 void sim_t::set_log(bool value)
 128 {
 129   log = value;
 130 }
 131
 132 void sim_t::set_histogram(bool value)
 133 {
 134   histogram_enabled = value;
 135   for (size_t i = 0; i < procs.size(); i++) {
 136     procs[i]->set_histogram(histogram_enabled);
 137   }
 138 }
 139
 140 void sim_t::set_procs_debug(bool value)
 141 {
 142   for (size_t i=0; i< procs.size(); i++)
 143     procs[i]->set_debug(value);
 144 }
 145
 146 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 147 {
 148   if (addr + len < addr)
 149     return false;
 150   return bus.load(addr, len, bytes);
 151 }
 152
 153 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 154 {
 155   if (addr + len < addr)
 156     return false;
 157   return bus.store(addr, len, bytes);
 158 }
 159
 160 void sim_t::make_config_string()
 161 {
 162   reg_t rtc_addr = IO_BASE;
 163   bus.add_device(rtc_addr, rtc.get());
 164
 165   uint32_t reset_vec[8] = {
 166     0x297 + MEM_BASE - DEFAULT_RSTVEC, // reset vector
 167     0x00028067,                        //   jump straight to MEM_BASE
 168     0x00000000,                        // reserved
 169     0,                                 // pointer to configuration string
 170     0, 0, 0, 0                         // trap vector
 171   };
 172   config_string_addr = DEFAULT_RSTVEC + sizeof(reset_vec);
 173   reset_vec[3] = config_string_addr;
 174
 175   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 176
 177   std::stringstream s;
 178   s << std::hex <<
 179         "platform {\n"
 180         "  vendor ucb;\n"
 181         "  arch spike;\n"
 182         "};\n"
 183         "rtc {\n"
 184         "  addr 0x" << rtc_addr << ";\n"
 185         "};\n"
 186         "ram {\n"
 187         "  0 {\n"
 188         "    addr 0x" << MEM_BASE << ";\n"
 189         "    size 0x" << (MEM_BASE + memsz) << ";\n"
 190         "  };\n"
 191         "};\n"
 192         "core {\n";
 193   for (size_t i = 0; i < procs.size(); i++) {
 194     s <<
 195         "  " << i << " {\n"
 196         "    " << "0 {\n" << // hart 0 on core i
 197         "      isa " << procs[i]->isa_string << ";\n"
 198         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 199         "    };\n"
 200         "  };\n";
 201   }
 202   s <<  "};\n";
 203
 204   config_string = s.str();
 205   rom.insert(rom.end(), config_string.begin(), config_string.end());
 206   rom.push_back(0);
 207   boot_rom.reset(new rom_device_t(rom));
 208   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 209 }